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參數(shù)資料
| 型號(hào)： | IDT82V2108PXG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁(yè)數(shù)： | 224/292頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FRAMER T1/J1/E1 8CH 128-PQFP |
| 標(biāo)準(zhǔn)包裝： | 500 |
| 控制器類型： | T1/E1/J1 調(diào)幀器 |
| 接口： | 并聯(lián) |
| 電源電壓： | 2.97 V ~ 3.63 V |
| 電流 - 電源： | 160mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 128-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 128-PQFP（14x20） |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 82V2108PXG8 |
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IDT82V2108
T1 / E1 / J1 OCTAL FRAMER
Functional Description
27
March 5, 2009
3.9.2
T1/J1 MODE
When the frame is synchronized, the signaling is located in the Bit 8
of Frame 6 (A bit) and Frame 12 (B bit) in SF format, and is located in
the Bit 8 of Frame 6 (A bit), Frame 12 (B bit), Frame 18 (C bit) and
signaling format is chosen by the ESF (b2, T1/J1-040H).
When the RSCKn/RSSIGn/MRSSIG[1:2] pins are used as the sig-
naling output, i.e. in Receive Clock Slave External Signaling mode or in
Receive Multiplex mode, the signaling codeword (AB or ABCD) is
clocked out in the lower nibble of the channel with its corresponding data
serializing on the RSDn/MRSD[1:2] pins (as shown in the Figure - 6).
However, in SF format, the signaling C and D are the repetition of signal-
ing A and B.
When the COSS (b6, T1/J1-040H) bit is logic 1, all the COSS[24:1]
(b7~0, T1/J1-041H and b7~0, T1/J1-042H and b7~0, T1/J1-043H) in the
Receive CAS/RBS Buffer registers will reflect the change of the signal-
ing of each channel respectively.
When the COSS (b6, T1/J1-040H) bit is logic 0, the Receive CAS/
RBS Buffer indirect registers (from 01H to 58H of RCRB indirect regis-
ters) can be accessed by the microprocessor. The address of the indi-
rect register is specified by the A[6:0] (b6~0, T1/J1-042H). Whether the
data is read from or written into the specified indirect register is deter-
mined by the R/WB (b7, T1/J1-042H) and the data is in the D[7:0] (b7~0,
T1/J1-043H). The indirect registers have a read/write cycle. Before the
read/write operation is completed, the BUSY (b7, T1/J1-041H) will be
set. New operations on the indirect registers can only be done when the
BUSY (b7, T1/J1-041H) is cleared. The read/write cycle is 650 ns.
The indirect registers are divided into three segments: two seg-
ments (from 01H to 18H & from 21H to 38H) contain the signaling bits of
each channel; another segment (from 41H to 58H) contains the signal-
ing debounce configuration of each channel.
A three-superframe capacity buffer is used for signaling debounce
and signaling freezing.
Signaling debounce will be performed by setting the DEB (b0, T1/
J1-RCRB-indirect registers - 41~58H). The DEB (b0, T1/J1-RCRB-indi-
rect registers - 41~58H) is activated when the PCCE (b0, T1/J1-040H) is
set. The signaling bits are updated only when 2 consecutive SF/ESF sig-
naling bits of a channel are the same.
Signaling freeze will remain the signaling automatically when it is
out of SF/ESF sync or in unframed mode.
The signaling bits are extracted to the A, B, C, D (b3~0, T1/J1-
RCRB-indirect registers - 01~18H or b3~0, T1/J1-RCRB-indirect regis-
ters - 21~38H).
There is a maximum 2 ms delay between the transition of the
COSS[n] (T1/J1-041H and T1/J1-042H and T1/J1-043H) and the updat-
ing of the A, B, C, D code in the corresponding indirect registers (b3~0,
T1/J1-RCRB-indirect registers - 21~38H). To avoid this 2 ms delay,
users can read the corresponding b3~0 in the T1/J1-RCRB-indirect reg-
isters - (01~18H) first. If the value of these four bits are different from the
previous A, B, C, D code, then the content of b3~0 in the T1/J1-RCRB-
indirect registers - (01~18H) is the updated A, B, C, D code. If the con-
tent of the four bits is the same as the previous A, B, C, D code, then
users should read the b3~0 in the T1/J1-RCRB-indirect registers -
(21~38H) to get the updated A, B, C, D code.
Any one of the 24-channels signaling change will cause an interrupt
on the INT pin if the SIGE (b5, T1/J1-040H) is set.
Figure 8. Signaling Output in T1/J1 Mode
Channel 24
Channel 1
Channel 2
Channel 24
A B C D
RSDn/
MRSD[1:2]
RSSIGn/
MRSSIG[1:2]
F
1 2 3 4 5 6 7 8
Channel 1
F
F-bit or Parity
1 2 3 4 5 6 7 81 2 3 4 5 6 7 8
A B C D
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