參數(shù)資料
型號: IDT82V2051EPPG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 61/61頁
文件大?。?/td> 0K
描述: IC LIU E1 SGL SHORT HAUL 44-TQFP
標(biāo)準(zhǔn)包裝: 80
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 44-LQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 托盤
其它名稱: 82V2051EPPG
IDT82V2051E
SINGLE CHANNEL E1 SHORT HAUL LINE INTERFACE UNIT
Pin Description
9
December 9, 2005
Notes:
1. TCLK missing: the state of TCLK continues to be high level or low level over 70 MCLK cycles.
2
PIN DESCRIPTION
Table-1 Pin Description
Name
Type
Pin No.
Description
TTIP
TRING
Analog
output
37
36
TTIP/TRING: Transmit Bipolar Tip/Ring
These pins are the differential line driver outputs. They will be in high impedance state under the following conditions:
THZ pin is high;
THZ bit is set to 1;
Loss of MCLK;
Loss of TCLK (exceptions: Remote Loopback; transmit internal pattern by MCLK);
Transmit path power down;
After software reset; pin reset and power on.
RTIP
RRING
Analog
input
41
40
RTIP/RRING: Receive Bipolar Tip/Ring
These signals are the differential receiver inputs.
TD/TDP
TDN
I2
3
TD: Transmit Data
When the device is in single rail mode, the NRZ data to be transmitted is input on this pin. Data on TD pin is sampled into the
device on the active edge of TCLK and is encoded by AMI or HDB3 line code rules before being transmitted. In this mode, TDN
should be connected to ground.
TDP/TDN: Positive/Negative Transmit Data
When the device is in dual rail mode, the NRZ data to be transmitted for positive/negative pulse is input on these pins. Data
on TDP/TDN pin is sampled into the device on the active edge of TCLK. The line code in dual rail mode is as follows:
TCLK
I
1
TCLK: Transmit Clock input
This pin inputs a 2.048 MHz transmit clock. The transmit data at TD/TDP or TDN is sampled into the device on the active edge
of TCLK. If TCLK is missing1 and the TCLK missing interrupt is not masked, an interrupt will be generated.
RD/RDP
CV/RDN
O5
6
RD: Receive Data output
In single rail mode, this pin outputs NRZ data. The data is decoded according to AMI or HDB3 line code rules.
CV: Code Violation indication
In single rail mode, the BPV/CV code violation will be reported by driving the CV pin to high level for a full clock cycle. HDB3
line code violation can be indicated if the HDB3 decoder is enabled. When AMI decoder is selected, bipolar violation will be indi-
cated.
In hardware control mode, the EXZ, BPV/CV errors in received data stream are always monitored by the CV pin if single rail
mode is chosen.
RDP/RDN: Positive/Negative Receive Data output
In dual rail mode, this pin outputs the re-timed NRZ data when CDR is enabled, or directly outputs the raw RZ slicer data if CDR
is bypassed.
Active edge and level select:
Data on RDP/RDN or RD is clocked with either the rising or the falling edge of RCLK. The active polarity is also selectable.
RCLK
O
4
RCLK: Receive Clock output
This pin outputs a 2.048 MHz receive clock. Under LOS condition with AIS enabled (bit AISE=1), RCLK is derived from MCLK.
In clock recovery mode, this signal provides the clock recovered from the RTIP/RRING signal. The receive data (RD in single
rail mode or RDP and RDN in dual rail mode) is clocked out of the device on the active edge of RCLK. If clock recovery is
bypassed, RCLK is the exclusive OR (XOR) output of the dual rail slicer data RDP and RDN. This signal can be used in appli-
cations with external clock recovery circuitry.
TDP
TDN
Output Pulse
0
Space
0
1
Positive Pulse
1
0
Negative Pulse
1
Space
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