參數(shù)資料
型號(hào): IDT82V2048EDR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 38/76頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 8CH SHORT 208-TQFP
標(biāo)準(zhǔn)包裝: 12
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 208-BFQFP
供應(yīng)商設(shè)備封裝: 208-PQFP(28x28)
包裝: 托盤
其它名稱: 82V2048EDR
43
INDUSTRIAL
TEMPERATURE RANGES
OCTAL CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
4.2.4
RECEIVE PATH CONTROL REGISTERS
Table-33 RCF0: Receiver Configuration Register 0
(R/W, Address = 07H,27H,47H,67H,87H,A7H,C7H,E7H)
Symbol
Bit
Default
Description
-
7-5
000
Reserved
R_OFF
4
0
Receiver power down enable
= 0: Receiver power up
= 1: Receiver power down
RD_INV
3
0
Receive data invert
= 0: data on RDn or RDPn/RDNn is active high
= 1: data on RDn or RDPn/RDNn is active low
RCLK_SEL
2
0
Receive clock edge select (this bit is ignored in slicer mode)
= 0: data on RDn or RDPn/RDNn is updated on the rising edges of RCLKn
= 1: data on RDn or RDPn/RDNn is updated on the falling edges of RCLKn
R_MD[1:0]
1-0
00
Receiver path decoding selection
= 00: receive data is HDB3 (E1) / B8ZS (T1/J1) decoded and output on RDn with single rail NRZ format
= 01: receive data is AMI decoded and output on RDn with single rail NRZ format
= 10: decoder is bypassed, re-timed dual rail data with NRZ format output on RDPn/RDNn (dual rail mode with
clock recovery)
= 11: both CDR and decoder blocks are bypassed, slicer data with RZ format output on RDPn/RDNn (slicer mode)
Table-34 RCF1: Receiver Configuration Register 1
(R/W, Address = 08H,28H,48H,68H,88H,A8H,C8H,E8H)
Symbol
Bit
Default
Description
-7
0
Reserved
EQ_ON
6
0
= 0: receive equalizer off
= 1: receive equalizer on (LOS programming enabled)
-
5
0
Reserved. Should be 0 for normal operation.
LOS[4:0]
4-0
10101
LOS Clear Level (dB)
LOS Declare Level (dB)
00000
0
<-4
00001
>-2
<-6
00010
>-4
<-8
00011
>-6
<-10
00100
>-8
<-12
00101
>-10
<-14
00110
>-12
<-16
00111
>-14
<-18
01000
>-16
<-20
01001
>-18
<-22
01010
>-20
<-24
01011 - 11111
Reserved
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