參數(shù)資料
型號: IDT82V2044EPFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 44/73頁
文件大?。?/td> 0K
描述: IC LIU T1/E1 QUAD SHORT 128-TQFP
標(biāo)準(zhǔn)包裝: 15
類型: 線路接口裝置(LIU)
規(guī)程: E1
電源電壓: 3.13 V ~ 3.47 V
安裝類型: 表面貼裝
封裝/外殼: 128-LQFP
供應(yīng)商設(shè)備封裝: 128-TQFP(14x20)
包裝: 托盤
其它名稱: 82V2044EPFG
49
INDUSTRIAL
TEMPERATURE RANGES
QUAD CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
4.2.8
INTERRUPT STATUS REGISTERS
Table-47 INTS0: Interrupt Status Register 0
(this register is reset after a read operation) (R, Address = 16H, 56H,96H, D6H)
Symbol
Bit
Default
Description
-7
0
Reserved
IBLBA_IS
6
0
This bit indicates the occurrence of the Inband Loopback Activate Code interrupt event.
= 0: no Inband Loopback Activate Code interrupt event occurred
= 1: Inband Loopback Activate Code Interrupt event occurred
IBLBD_IS
5
0
This bit indicates the occurrence of the Inband Loopback Deactivate Code interrupt event.
= 0: no Inband Loopback Deactivate Code interrupt event occurred
= 1: interrupt event of the received inband loopback deactivate code occurred.
PRBS_IS
4
0
This bit indicates the occurrence of the interrupt event generated by the PRBS/QRSS synchronization status.
= 0: no PRBS/QRSS synchronization status interrupt event occurred
= 1: PRBS/QRSS synchronization status interrupt event occurred
TCLK_LOS_IS
3
0
This bit indicates the occurrence of the interrupt event generated by the TCLKn loss detection.
= 0: no TCLKn loss interrupt event.
= 1:TCLKn loss interrupt event occurred.
DF_IS
2
0
This bit indicates the occurrence of the interrupt event generated by the Driver Failure.
= 0: no Driver Failure interrupt event occurred
= 1: Driver Failure interrupt event occurred
AIS_IS
1
0
This bit indicates the occurrence of the AIS (Alarm Indication Signal) interrupt event.
= 0: no AIS interrupt event occurred
= 1: AIS interrupt event occurred
LOS_IS
0
This bit indicates the occurrence of the LOS (Loss of signal) interrupt event.
= 0: no LOS interrupt event occurred
= 1: LOS interrupt event occurred
Table-48 INTS1: Interrupt Status Register 1
(this register is reset and relevant interrupt request is cleared after a read) (R, Address = 17H, 57H,97H, D7H)
Symbol
Bit
Default
Description
DAC_OV_IS
7
0
This bit indicates the occurrence of the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event.
= 0: no pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
= 1: the pulse amplitude overflow of Arbitrary Waveform Generator interrupt event occurred
JAOV_IS
6
0
This bit indicates the occurrence of the Jitter Attenuator Overflow interrupt event.
= 0: no JA overflow interrupt event occurred
= 1: A overflow interrupt event occurred
JAUD_IS
5
0
This bit indicates the occurrence of the Jitter Attenuator Underflow interrupt event.
= 0: no JA underflow interrupt event occurred
= 1: JA underflow interrupt event occurred
ERR_IS
4
0
This bit indicates the occurrence of the interrupt event generated by the detected PRBS/QRSS logic error.
= 0: no PRBS/QRSS logic error interrupt event occurred
= 1: PRBS/QRSS logic error interrupt event occurred
EXZ_IS
3
0
This bit indicates the occurrence of the Excessive Zeros interrupt event.
= 0: no excessive zeros interrupt event occurred
= 1: EXZ interrupt event occurred
CV_IS
2
0
This bit indicates the occurrence of the Code Violation interrupt event.
= 0: no code violation interrupt event occurred
= 1: code violation interrupt event occurred
TMOV_IS
1
0
This bit indicates the occurrence of the One-Second Timer Expiration interrupt event.
= 0: no one-second timer expiration interrupt event occurred
= 1: one-second timer expiration interrupt event occurred
CNT_OV_IS
0
This bit indicates the occurrence of the Counter Overflow interrupt event.
= 0: no counter overflow interrupt event occurred
= 1: counter overflow interrupt event occurred
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