參數(shù)資料
型號： IDT82V2041EPPG
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 32/75頁
文件大小： 0K
描述： IC LIU T1/J1/E1 1CH 44-TQFP
標(biāo)準(zhǔn)包裝： 80
類型： 線路接口裝置（LIU）
規(guī)程： E1
電源電壓： 3.13 V ~ 3.47 V
安裝類型： 表面貼裝
封裝/外殼： 44-LQFP
供應(yīng)商設(shè)備封裝： 44-TQFP（10x10）
包裝： 托盤
其它名稱： 82V2041EPPG
IDT82V2041E
SINGLE CHANNEL T1/E1/J1 SHORT HAUL LINE INTERFACE UNIT
Programming Information
38
December 9, 2005
4.3
REGISTER DESCRIPTION
4.3.1
CONTROL REGISTERS
Table-20 ID: Device Revision Register
(R, Address = 00H)
Symbol
Bit
Default
Description
ID[7:0]
7-0
00H
Current silicon chip ID.
Table-21 RST: Reset Register
(W, Address = 01H)
Symbol
Bit
Default
Description
RST[7:0]
7-0
00H
Software reset. A write operation on this register will reset all internal registers to their default values, and the status
of all ports are set to the default status. The content in this register can not be changed. After reset, all drivers output
are in high impedance state.
Note: Bit T1E1 (GCF0) will keep set value and will not be reset.
Table-22 GCF: Global Configuration Register
(R/W, Address = 02H)
Symbol
Bit
Default
Description
-
7-3
00000
Reserved.
T1E1
2
0
This bit selects the E1 or T1/J1 operation mode globally.
= 0: E1 mode is selected.
= 1: T1/J1 mode is selected.
Note: After bit T1E1 is changed: Before accessing any other regisers a delay of 50us is required to allow the internal clocking
to be settled.
INT_PIN[1:0]
1-0
00
Interrupt pin control
= x0: Open drain, active low (with an external pull-up resistor)
= 01: Push-pull, active low
= 11: Push-pull, active high
Table-23 TERM: Transmit and Receive Termination Configuration Register
(R/W, Address = 03H)
Symbol
Bit
Default
Description
-
7-6
00
Reserved.
T_TERM[2:0]
5-3
000
These bits select the internal termination for transmit line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010: Internal 100
impedance matching
= 011: Internal 110
impedance matching
= 1xx: Selects external impedance matching resistors for E1 mode only. T1/J1 does not require external impedance
resistors (see Table-10).
R_TERM[2:0]
2-0
000
These bits select the internal termination for receive line impedance matching.
= 000: Internal 75
impedance matching
= 001: Internal 120
impedance matching
= 010: Internal 100
impedance matching
= 011: Internal 110
impedance matching
= 1xx: Selects external impedance matching resistors (see Table-11).
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