參數(shù)資料
型號(hào)： IDT82P2284BB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： Quad T1/E1/J1 Long Haul / Short Haul Transceiver
中文描述： DATACOM, PCM TRANSCEIVER, PBGA208
封裝： PLASTIC, BGA-208
文件頁(yè)數(shù)： 73/375頁(yè)
文件大小： 2430K
代理商： IDT82P2284BB
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IDT82P2281
SINGLE T1/E1/J1 LONG HAUL / SHORT HAUL TRANSCEIVER
62
October 7, 2003
Figure 26. E1 To T1/J1 Format Mapping - Continuous Channels Mode
In the Transmit Clock Slave mode, the timing signal on the TSCK
pin and the framing pulse on the TSFS pin to input the data on the TSD
pin are provided by the system side. The signaling bits on the TSIG pin
are per-channel aligned with the data on the TSD pin.
In the Transmit Clock Slave mode, the data on the system interface
is clocked by the TSCK. The active edge of the TSCK used to sample
the pulse on the TSFS is determined by the FE bit. The active edge of
the TSCK used to sample the data on the TSD and TSIG is determined
by the DE bit. If the FE bit and the DE bit are not equal, the pulse on the
TSFS is ahead. The data rate of the system side is 1.544 Mb/s or 2.048
Mb/s. When it is 2.048 Mb/s, the TSCK can be selected by the CMS bit
to be the same rate as the data rate on the system side (2.048 MHz) or
double the data rate (4.096 MHz). If the speed of the TSCK is double the
data rate, there will be two active edges in one bit duration. In this case,
the EDGE bit determines the active edge to sample the data on the TSD
and TSIG pins. The pulse on the TSFS pin is always sampled on its first
active edge.
In the Transmit Clock Slave mode, the TSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
TSFS is selected by the FSINV bit. If the pulse on the TSFS pin is not an
integer multiple of 125
μ
s, this detection will be indicated by the TCOFAI
bit. If the TCOFAE bit is enabled, an interrupt will be reported by the
INT
pin when the TCOFAI bit is ‘1’.
3.18.1.3
Transmit Multiplexed Mode
In the Transmit Multiplexed mode, since the demultiplexed data
rate on the system side (2.048 Mb/s) should be mapped to the data rate
in the line side (1.544 Mb/s), 3 kinds of schemes should be selected by
the MAP[1:0] bits. The schemes per G.802, per One Filler Every Four
CHs and per Continuous CHs are the same as the description in
Chapter 3.18.1.2 Transmit Clock Slave Mode.
In the Transmit Multiplexed mode, one multiplexed bus is used to
transmit the data to the link. The data of the link is byte-interleaved input
from the multiplexed bus. When the data on the multiplexed bus is input
to the link, the position of the data is arranged by setting the channel off-
set.
In the Transmit Multiplexed mode, the timing signal on the MTSCK
pin and the framing pulse on the MTSFS pin are provided by the system
side. The signaling bits on the MTSIG pin are per-channel aligned with
the corresponding data on the MTSD pin.
In the Transmit Multiplexed mode, the data on the system interface
is clocked by the MTSCK. The active edge of the MTSCK used to sam-
ple the pulse on the MTSFS is determined by the FE bit. The active
edge of the MTSCK used to sample the data on the MTSD and MTSIG
is determined by the DE bit. If the FE bit and the DE bit are not equal,
the pulse on the MTSFS is ahead. The MTSCK can be selected by the
CMS bit to be the same rate as the data rate on the system side (8.192
MHz) or double the data rate (16.384 MHz). If the speed of the MTSCK
is double the data rate, there will be two active edges in one bit duration.
In this case, the EDGE bit determines the active edge to sample the
data on the MTSD and MTSIG pins. The pulse on the MTSFS pin is
always sampled on its first active edge.
In the Transmit Multiplexed mode, the MTSFS can indicate each F-
bit or the first F-bit of every SF/ESF/T1 DM/SLC-96 multi-frame. The
indications are selected by the FSTYP bit. The active polarity of the
MTSFS is selected by the FSINV bit. If the pulse on the MTSFS pin is
not an integer multiple of 125
μ
s, this detection will be indicated by the
TCOFAI bit. If the TCOFAE bit is enabled, an interrupt will be reported by
the
INT
pin when the TCOFAI bit is ‘1’.
3.18.1.4
Offset
Bit offset and channel offset are both supported in all the operating
modes. The offset is between the framing pulse on the TSFS/MTSFS
pin and the start of the corresponding frame input on the TSD/MTSD
pin. The signaling bits on the TSIG/MTSIG pin are always per-channel
aligned with the data on the TSD/MTSD pin.
Figure 27 to Figure 30 show the base line without offset.
1.544
Mb/s
2.048
Mb/s
CH1
CH2
CH3
F
CH23
CH1
CH2
CH24
TS0
TS2
TS1
TS23
TS24
TS0
TS1
TS2
TS24
the 8th bit
CH24
TS3
TS25~TS31
the 8th bit
F
F
CH1
discarded
discarded
discarded
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