參數(shù)資料
型號： IDT821054A
廠商： Integrated Device Technology, Inc.
元件分類： Codec
英文描述： QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
中文描述： 四可編程PCM編解碼器的MPI接口
文件頁數(shù)： 15/42頁
文件大?。?/td> 512K
代理商： IDT821054A
15
IDT821054A QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE INDUSTRIAL TEMPERATURE
3
OPERATING THE IDT821054A
3.1
PROGRAMMING DESCRIPTION
The IDT821054A is programmed by writing commands to registers
and coefficient RAM. A Channel Program Enable register (GREG6) is
provided for addressing individual or multiple channels. The CE[3:0] bits
in this register are assigned to Channel 4 to Channel 1 respectively. The
channels are enabled to be programmed by setting their respective CE
bits to ‘1’. If two or more channels are enabled, the successive write
commands will be effective to all enabled channels. A broadcast mode
can be implemented by simply enabling all four channels before
performing other write-operation. The broadcast mode is very useful for
configuring the coefficient RAM of the IDT821054A in a large system.
But for read operations, multiple addressing is not allowed.
The IDT821054A uses an Identification Code to distinguish itself
from other devices in the system. When being read, the IDT821054A will
output an Identification Code of 81H first to indicate that the following
data bytes are from the IDT821054A.
3.1.1
COMMAND TYPE AND FORMAT
The IDT821054A provides three types of commands as follows:
Local Command (LC), which is used to address the local registers of
the specified channel(s).
Global Command (GC), which is used to address the global registers
of all four channels.
RAM Command (RC), which is used to address the coefficient RAM
(Coe-RAM).
The format of the command is as the following:
R
/W:
Read/Write Command bit
b7 = 0:
b7 = 1:
Command Type
b6 b5 = 00: LC - Local Command
b6 b5 = 01: GC - Global Command
b6 b5 = 10: Not Allowed
b6 b5 = 11: RC - RAM Command
Address: b[4:0], specify one or more local/global registers or a block
of Coe-RAM to be addressed.
For Local Command and Global Command, the b[4:0] bits are used
to specify the address of the local registers and global registers
respectively.
For RAM Command, b[4:0] bits are used to specify the block of the
Coe-RAM.
Read Command
Write Command
CT:
3.1.2
ADDRESSING THE LOCAL REGISTERS
When addressing the local registers, users must specify which
channel(s) will be addressed first. If two or more channels are specified
via GREG6, the corresponding local registers of the specified channels
will be addressed by a Local Command at the same time.
The IDT821054A provides a consecutive adjacent addressing
method for accessing the local registers. According to the address
specified in a Local Command, there will be 1 to 4 adjacent local
registers to be addressed automatically, with the highest order first. For
example, if the address specified in a Local Command ends with ‘11’
(b1b0 = 11), 4 adjacent registers will be addressed by this command; if
b1b0 = 10, 3 adjacent registers will be addressed. See
Table - 1
for
details.
Table - 1 Consecutive Adjacent Addressing
When addressing local registers, the procedure of consecutive
adjacent addressing can be stopped by the
CS
signal at any time. If
CS
is changed from low to high, the operation to the current register and the
next adjacent registers will be aborted. However, the previous operation
results will not be affected.
3.1.3
ADDRESSING THE GLOBAL REGISTERS
For global registers are shared by all four channels, it is no need to
specify the channel(s) before addressing a global register. Except for
this, the global registers are addressed in a similar way as local
registers. The procedure of consecutive adjacent addressing can be
stopped by the
CS
signal at any time.
3.1.4
ADDRESSING THE COE-RAM
There are totally 40 words of Coe-RAM. They are divided to 5
blocks. Each block consists of 8 words. Each word is 14-bit wide.
The 5 blocks of the Coe-RAM are assigned for different filter
coefficients as shown below (refer to
“9 Appendix: IDT821054A Coe-
RAM Mapping”
for the address of the Coe-RAM):
Block 1: IMF RAM (Word 0 - Word 7), containing the Impedance
Matching Filter coefficient.
Block 2: ECF RAM (Word 8 - Word 15), containing the Echo
Cancellation Filter coefficient.
Block 3: GIS RAM (Word 16 - Word 19) and Tone Generator RAM
(Word 20 - Word 23), containing the Gain of Impedance Scaling and
dual tone coefficients.
Block 4: FRX RAM (Word 24 - Word 30) and GTX RAM (Word 31),
containing the coefficient of the Frequency Response Correction in
Transmit Path and the Gain in Transmit Path;
Block 5: FRR RAM (Word 32 - Word 38) and GRX RAM (Word 39),
containing the coefficient of the Frequency Response Correction in
Receive Path and the Gain in Receive Path.
The Coe-RAM blocks used for containing the IMF, ECF, GIS, FRX,
GTX, FRR and GRX coefficients are shared by all four channels. When
coefficients are written to these blocks, they will be used by all four
channels. But the four words (word 20 to 23), which contain the dual
b7
b6
b5
b4
b3
b2
b1
b0
R
/W
CT
Address
Address Specified in a Local
Command
In/Out Data
Bytes
byte 1
byte 2
byte 3
byte 4
byte 1
byte 2
byte 3
byte 1
byte 2
Address of the Local
Registers to be accessed
XXX11
XXX10
XXX01
XXX00
XXX10
XXX01
XXX00
XXX01
XXX00
b[4:0] = XXX11
(b1b0 = 11, four bytes of data)
b[4:0] = XXX10
(b1b0 = 10, three bytes of data)
b[4:0] = XXX01
(b1b0 = 01, two bytes of data)
b[4:0] = XXX00
(b1b0 = 00, one byte of data)
byte 1
XXX00
相關PDF資料
PDF描述
IDT821054APF QUAD PROGRAMMABLE PCM CODEC WITH MPI INTERFACE
IDTAS4624 0.5ヘ LOW VOLTAGE, SINGLE SPDT ANALOG SWITCH
IDTAS4624DZG 0.5ヘ LOW VOLTAGE, SINGLE SPDT ANALOG SWITCH
IDTAS4684NBG 0.5 OHM, DUAL SPDT ANALOG SWITCH
IDTAS4684NBG8 0.5 OHM, DUAL SPDT ANALOG SWITCH
相關代理商/技術參數(shù)
參數(shù)描述
IDT821054APF 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054APF8 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054APFG 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054APFG8 功能描述:IC PCM CODEC QUAD MPI 64-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
IDT821054PQF 功能描述:IC PCM CODEC QUAD MPI 64-PQFP RoHS:否 類別:集成電路 (IC) >> 接口 - 編解碼器 系列:- 標準包裝:2,500 系列:- 類型:立體聲音頻 數(shù)據(jù)接口:串行 分辨率（位）:18 b ADC / DAC 數(shù)量:2 / 2 三角積分調(diào)變:是 S/N 比，標準 ADC / DAC (db):81.5 / 88 動態(tài)范圍，標準 ADC / DAC (db):82 / 87.5 電壓 - 電源，模擬:2.6 V ~ 3.3 V 電壓 - 電源，數(shù)字:1.7 V ~ 3.3 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:48-WFQFN 裸露焊盤 供應商設備封裝:48-TQFN-EP（7x7） 包裝:帶卷 (TR)
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