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參數(shù)資料
| 型號： | IDT7MPV6255S15M |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 256KB AND 512KB SECONDARY CACHE MODULES FOR THE PowerPCO |
| 中文描述： | 256KB和512KB的庫PowerPCO二級緩存模塊 |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 84K |
| 代理商： | IDT7MPV6255S15M |
IDT7MPV6253/55/56
256KB/512KB CMOS SECONDARY CACHE MODULES FOR THE PowerPC
COMMERCIAL TEMPERATURE RANGE
3
FUNCTIONAL BLOCK DIAGRAM
IDT7MPV6256 – 512KB PIPELINED BURST VERSION
drw 03
CAPACITANCE (IDT7MPV6253 )
(1)
(T
A
= +25
°
C, f = 1.0 MHz)
Symbol
Parameter
(1)
C
IN1
Input Capacitance
(Address)
C
IN2
Input Capacitance
(ADDR
0-1
)
C
IN3
Input Capacitance
(OE#)
C
IN4
Input Capacitance
(WE#, TWE#)
C
I/O
I/O Capacitance
Condition
V
IN
= 0V
Max.
15
Unit
pF
V
IN
= 0V
25
pF
V
IN
= 0V
45
pF
V
IN
= 0V
8
pF
V
OUT
= 0V
10
pF
NOTES:
1. These parameters are guaranteed by design but not tested.
tbl 05
CAPACITANCE (IDT7MPV6255/56 )
(1)
(T
A
= +25
°
C, f = 1.0 MHz)
Symbol
Parameter
(1)
C
IN1
Input Capacitance
(Address)
C
IN2
Input Capacitance
(ADDR
0-1
)
C
IN3
Input Capacitance
(OE#)
C
IN4
Input Capacitance
(WE#, TWE#)
C
I/O
I/O Capacitance
Condition
V
IN
= 0V
Max.
20
Unit
pF
V
IN
= 0V
—
pF
V
IN
= 0V
15
pF
V
IN
= 0V
8
pF
V
OUT
= 0V
10/20
pF
NOTES:
1. These parameters are guaranteed by design but not tested.
tbl 06
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
WE#
0
WE#
1
WE#
2
WE#
3
CLK
1
WE#
4
WE#
5
WE#
6
WE#
7
CLK
0
16K x 12
Tag Field
16K x 2
Status
A
1
- A
12
12
TMATCH
DIRTYOUT
A
13
- A
2614
TWE#
TOE#
STANDBY
TCLR#
TVALID
DIRTYIN
CLK
2
DH
0
-
31
32
DL
0
-
31
32
32K x 32
Pipelined
Burst
SRAM
32K x 32
Pipelined
Burst
SRAM
DL
0
-
31
32
DH
0
-
31
32
WE#
0
WE#
1
WE#
2
WE#
3
CLK
1
WE#
4
WE#
5
WE#
6
WE#
7
CLK
0
SRAM OE#0
SRAM ADS#0
CNT EN#0
STANDBY
BURST MODE
SRAM OE#1
SRAM ADS#1
CNT EN#1
STANDBY
BURST MODE
A
13
- A
28
16
PD
2
PD
3
PD
0
PD
1
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