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參數(shù)資料
| 型號(hào)： | IDT7MP4095 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Octal Bus Transceivers with 3-State Outputs 20-SOIC -40 to 85 |
| 中文描述： | 128K的× 32的CMOS靜態(tài)RAM模塊 |
| 文件頁(yè)數(shù)： | 6/8頁(yè) |
| 文件大小： | 96K |
| 代理商： | IDT7MP4095 |
IDT7MP4060/7MP4095
128K x 32 CMOS STATIC RAM MODULES
COMMERCIAL TEMPERATURE RANGE
7.09
6
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
NOTES:
1.
WE
or
CS
must be high during all address transitions.
2. A write occurs during the overlap (t
WP
) of a low
CS
and a low
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going high to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
low transition occurs simultaneously with or after the
WE
low transition, the outputs remain in a high impedance state.
6. Transition is measured
±
200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE
is low during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP or (
t
WHZ +
t
DW)
.
CS
3147 drw 08
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
DATA VALID
CS
3147 drw 07
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WHZ
t
OHZ
(6)
(6)
(4)
(4)
(7)
(6)
t
OW
OE
(6)
t
OHZ
DATA VALID
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7MP4095S15M | Octal Bus Transceivers with 3-State Outputs 20-SOIC -40 to 85 |
| IDT7MP4095S15Z | Octal Bus Transceivers with 3-State Outputs 20-BGA MICROSTAR JUNIOR -40 to 85 |
| IDT7MP4095S20M | Octal Bus Transceivers with 3-State Outputs 20-PDIP -40 to 85 |
| IDT7MP4095S20Z | Octal Bus Transceivers with 3-State Outputs 20-PDIP -40 to 85 |
| IDT7MP4060 | 128K x 32 CMOS STATIC RAM MODULES |
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