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參數(shù)資料
| 型號： | IDT7MMV4101S10BG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 24 Three Megabit 3.3V CMOS Static RAM |
| 中文描述： | 128K X 24 STANDARD SRAM, 10 ns, PBGA119 |
| 封裝： | PLASTIC, BGA-119 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大小： | 86K |
| 代理商： | IDT7MMV4101S10BG |
6
IDT7MMV4101
128K x 24 Three Megabit 3.3V CMOS Static RAM Commercial and Industrial Temperature Ranges
Timing Waveform of Write Cycle No. 1 (
WE
Controlled Timing)
(1,4,5)
Timing Waveform of Write Cycle No. 2 (
CS
Controlled Timing)
(1, 4)
CS
ADDRESS
DATA
IN
4083 drw 07
t
AW
t
WC
t
CW
t
AS
t
WR
t
DW
t
DH
DATA
IN
VALID
WE
(3)
.
NOTES:
1. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
2.
OE
is continuously HIGH. During a
WE
controlled write cycle with
OE
LOW, t
WP
must be greater than or equal to t
WHZ
+ t
DW
to allow the I/O drivers to turn off and
data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the mnimumwrite pulse
is the specified t
WP
.
3. During this period, I/O pins are in the output state, and input signals must not be applied.
4. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high impedance state.
CS
must be active during the t
CW
write period.
5. Transition is measured ±200mV fromsteady state.
ADDRESS
CS
WE
DATA
OUT
DATA
IN
4083 drw 06
(3)
DATA
IN
VALID
HIGH IMPEDANCE
t
WC
t
AW
t
AS
t
WHZ
t
WP
t
CHZ
t
OW
t
DW
t
DH
t
WR
(4)
(4)
.
(5)
(5)
(5)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7MMV4101S12BG | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| IDT7MMV4101S12BGI | Octal Buffers/Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| IDT7MMV4101S15BG | Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85 |
| IDT7MMV4101S15BGI | Octal Buffers/Drivers With 3-State Outputs 20-SO -40 to 85 |
| IDT7MP4060S20Z | Octal Bus Transceivers with 3-State Outputs 20-SOIC -40 to 85 |
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