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參數(shù)資料
| 型號(hào)： | IDT7MB4048 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | IC LOGIC 244 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS -40+85C SOIC-20 38/TUBE |
| 中文描述： | 為512k × 8的CMOS靜態(tài)RAM模塊 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大小： | 80K |
| 代理商： | IDT7MB4048 |
7.11
5
IDT7MB4048
512K x 8 CMOS STATIC RAM MODULE
COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS
CONTROLLED TIMING)
(1, 2, 3, 5)
CS
2675 drw 09
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
WP
t
DH
DATA
OUT
t
WHZ
t
OHZ(6)
(6)
(4)
(4)
(7)
(6)
t
OW
OE
(6)
t
OHZ
DATA VALID
CS
2675 drw 10
t
AW
t
AS
t
WR
t
DW
DATA
IN
ADDRESS
t
WC
WE
t
CW
t
DH
DATA VALID
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
CONTROLLED TIMING)
(1, 2, 3, 7)
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap (t
WP
) of a LOW
CS
and a LOW
WE
.
3. t
WR
is measured from the earlier of
CS
or
WE
going HIGH to the end of write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high-impedance state.
6. Transition is measured
±
200mV from steady state with a 5pF load (including scope and jig). This parameter is guaranteed by design, but not tested.
7. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
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