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參數(shù)資料
| 型號(hào)： | IDT7M1014S20GB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 4K x 36 BiCMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 4K X 36 MULTI-PORT DEVICE SRAM MODULE, 20 ns, CPMA142 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 85K |
| 代理商： | IDT7M1014S20GB |
7.03
5
IDT7M1014 4K x 36 BiCMOS
DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5V
±
10%, T
A
= –55
°
C to +125
°
C or 0
°
C to +70
°
C)
7M1014SxxG
7M1014SxxGB
-15
-20
-25
-30
Symbol Parameter
Read Cycle
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
t
RC
Read Cycle Time
15
—
20
—
25
—
30
—
ns
t
AA
Address Access Time
—
15
—
20
—
25
—
30
ns
t
OE
Output Enable Access Time
—
8
—
10
—
12
—
15
ns
t
OH
Output Hold from Address Change
3
—
3
—
3
—
3
—
ns
t
OLZ
(1)
Output Enable to Output in Low-Z
0
—
0
—
0
—
0
—
ns
t
OHZ
(1)
Output Disable to Output in Hi-Z
—
7
—
9
—
11
—
13
ns
Write Cycle
t
WC
Write Cycle Time
15
—
20
—
25
—
30
—
ns
t
AW
Address Valid to End of Write
14
—
15
—
20
—
25
—
ns
t
AS
Address Set-Up Time
0
—
0
—
0
—
0
—
ns
t
WP
Write Pulse Width
12
—
15
—
20
—
25
—
ns
t
WR
Write Recovery Time
1
—
2
—
2
—
2
—
ns
t
DW
Data Valid to End of Write
10
—
12
—
15
—
20
—
ns
t
DH
Data Hold Time
0
—
0
—
0
—
0
—
ns
t
WHZ
(1)
Write Enable to Output in Hi-Z
—
7
—
9
—
11
—
13
ns
t
OW
(1)
Output Active from End of Write
0
—
0
—
0
—
0
—
ns
t
WDD
Write Pulse to Data Delay
—
30
—
40
—
45
—
50
ns
t
DDD
(1)
Write Data Valid to Read Data Delay
—
25
—
30
—
35
—
40
ns
NOTES:
1. This parameter is guaranteed by design but not tested.
2. Port-to-Port delay through the RAM cells from the writing port to the reading port.
2819 tbl 09
NOTES:
1. R/
W
is HIGH for Read Cycles.
2.
OE
≤
V
IL.
TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)
(1,2)
2819 drw 05
t
AA
t
OH
t
RC
ADDRESS
DATA
OUT
t
OH
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