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參數(shù)資料
| 型號： | IDT7M1003S35CB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 64K X 8 MULTI-PORT DEVICE SRAM MODULE, 35 ns, DMA64 |
| 文件頁數(shù)： | 6/11頁 |
| 文件大?。?/td> | 171K |
| 代理商： | IDT7M1003S35CB |
7.5
6
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF READ CYCLE NO. 1 (EITHER SIDE)
(1,2,4)
2804 drw 06
ADDRESS
t
OH
t
RC
DATA
OUT
PREVIOUS DATA VALID
t
AA
t
OH
DATA VALID
TIMING WAVEFORM OF READ CYCLE NO. 2 (EITHER SIDE)
(1,3,5)
ACS
t
t
OE
t
CHZ(6)
t
OHZ(6)
t
PD(6)
50%
50%
t
PU(6)
CS
DATA
OUT
CURRENT
I
CC
I
SB
t
OLZ(6)
DATA VALID
t
CLZ(6)
OE
NOTES:
1. R/
W
is HIGH for Read Cycles
2. Device is continuously enabled.
CS
= LOW. This waveform cannot be used for semaphore reads.
3. Addresses valid prior to or coincident with
CS
transition LOW.
4.
OE
= LOW.
5. To access RAM,
CS
= LOW,
SEM
= H. To access semaphore,
CS
= HIGH and
SEM
= LOW.
6. This parameter is guaranteed by design but not tested.
2804 drw 07
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