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參數(shù)資料
| 型號： | IDT7M1003S35C |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 128K x 8 64K x 8 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 64K X 8 MULTI-PORT DEVICE SRAM MODULE, 35 ns, DMA64 |
| 文件頁數(shù)： | 8/11頁 |
| 文件大?。?/td> | 171K |
| 代理商： | IDT7M1003S35C |
7.5
8
IDT7M1001/1003
128K/64K x 8 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE TIMING (EITHER SIDE)
(1)
NOTE:
1.
CS
= HIGH for the duration of the above timing (both write and read cycle).
2804 drw 10
2804 drw 11
NOTES:
1. D
0R
= D
0L
= LOW, L_
CS
= R_
CS
= HIGH. Semaphore Flag is released form both sides (reads as ones from both sides) at cycle start.
2. "A" may be either left or right port. "B" is the opposite port from "A".
3. This parameter is measured from R/
W
A
or
SEM
A
going HIGH to R/
W
B
or
SEM
B
going HIGH.
4. If t
SPS
is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
t
AW
t
WR
t
ACS
t
AA
t
OH
t
WP
t
SOP
t
DW
t
AS
t
WP
t
DH
t
SWRD
t
OE
t
SOP
VALID ADDRESS
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
READ CYCLE
WRITE CYCLE
A
0
- A
2
SEM
DATA
0
R/W
OE
TIMING WAVEFORM OF SEMAPHORE CONTENTION
(1,3,4)
MATCH
MATCH
t
SPS
A
0A -
A
2A
R/W
SEM
A
A
A
0B -
A
2B
R/W
SEM
B
B
SIDE
(2)
“A”
SIDE
(2)
“B”
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