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參數(shù)資料
| 型號： | IDT7M1002S40GB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | 16K x 32 CMOS DUAL-PORT STATIC RAM MODULE |
| 中文描述： | 16K X 32 MULTI-PORT DEVICE SRAM MODULE, 40 ns, CPGA121 |
| 封裝： | CERAMIC, PGA-121 |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 166K |
| 代理商： | IDT7M1002S40GB |
7.02
8
IDT7M1002
16K x 32 CMOS DUAL-PORT STATIC RAM MODULE
MILITARY AND COMMERCIAL TEMPERATURE RANGES
2795 drw 09
t
DH
R/
W
SEM
t
AW
t
DW
t
SOP
t
WP
t
WP
t
AS
t
SWRD
t
AA
t
OH
t
WR
t
ACE
DATA
OUT
VALID
DATA
IN
VALID
t
AOE
t
SOP
READ CYCLE
WRITE CYCLE
VALID ADDRESS
VALID ADDRESS
OE
A
0
–A
2
DATA
0
TIMING WAVEFORM OF SEMAPHORE READ AFTER WRITE, EITHER SIDE
(1)
NOTE:
1.
CS
≥
V
IH
for the duration of the above timing (both write and read cycle).
TIMING WAVEFORM OF SEMAPHORE CONTENTION
(1, 3, 4)
SIDE "B"
(2)
2795 drw 10
MATCH
t
SPS
MATCH
SEM
B
A
0B
— A
2B
SIDE "A"
R/
W
B
SEM
A
A
0A
— A
2A
R/
W
A
NOTES:
1. D
OR
= D
OL
≤
V
IL,
(L_
CS
= R_
CS
)
≥
V
IH
Semaphore Flag is released from both sides (reads as ones from both sides) at cycle start.
2. “A” may be either left or right port. “B” is the opposite port from “A”.
3. This parameter is measured from R/
W
A
or
SEM
A
going HIGH to R/
W
B
or
SEM
B
going HIGH.
4. If tSPS is violated, the semaphore will fall positively to one side or the other, but there is no guarantee which side will obtain the flag.
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