參數(shù)資料
型號(hào): IDT79RC64V474-200DZ
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 21/25頁(yè)
文件大小: 0K
描述: IC MPU 64BIT EMB 200MHZ 128-QFP
標(biāo)準(zhǔn)包裝: 24
處理器類型: RISC 64-位
速度: 200MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 128-BQFP 裸露焊盤
供應(yīng)商設(shè)備封裝: 128-PQFP(28x28)
包裝: 托盤
其它名稱: 79RC64V474-200DZ
5 of 25
April 10, 2001
RC64474 RC64475
Serial
Bit
Description
Value & Mode Setting
255:18
Reserved
Must be 0
17:15
WAdrWData_Del
Write address to write data delay in Master-
Clock cycles.
000
→ 0 cycles
001
→ 1 cycle
010
→ 2 cycles
011
→ 3 cycles
100
→ 4 cycles
101
→ 5 cycles
110
→ 6 cycles
111
→ 7 cycles
14:13
Drv_Out
output driver slew rate control. Bit 14 is MSB.
Affects only non-clock outputs.
Output driver strength:
10
→ 100% strength (fastest)
11
→ 83% strength
00
→ 67% strength
01
→ 50% strength (slowest)
12
System interface bus width
0
→ 64-bit system interface
1
→ 32-bit system interface
11
TmrIntEn
Disables the timer interrupt on Int*[5]
0
→ Enabled Timer Interrupt
1
→ Disabled Timer Interrupt
10:9
Non-block write
Selects non-block write type. Bit 10 is MSB.
00
→ RC4x00 compatible
01
→ Reserved
10
→ Pipelined writes
11
→ Write re-issue
7:5
Clock
Multiplier
MasterClock is multiplied internally to gener-
ate PClock
Clock multiplier:
0 Multiply by 2
1 Multiply by 3
2 Multiply by 4
3 Multiply by 5
4 Multiply by 6
5 Multiply by 7
6 Multiply by 8
7 Reserved
8EndBit
Specifies byte ordering
0
→ Little endian
1
→ Big endian
4:1
Writeback data rate
System interface data rate for block writes
only: bit 4 is MSB
64-bit:
9:15 Reserved
8
→ dxxxdxxxdxxxdxxx
7
→ ddxxxxxxddxxxxxx
6
→ dxxdxxdxxdxx
5
→ ddxxxxddxxxx
4
→ ddxxxddxxx
3
→ dxdxdxdx
2
→ ddxxddxx
1
→ ddxddx
0
→ dddd
32-bit:
9:15 Reserved
8
→ wxxxwxxxwxxxwxxxwxxxwxxxwxxxwxxx
7
→ wwxxxxxxwwxxxxxxwwxxxxxxwwxxxxxx
6
→ wxxwxxwxxwxxwxxwxxwxxwxx
5
→ wwxxxxwwxxxxwwxxxxwwxxxx
4
→ wwxxxwwxxxwwxxxwwxxx
3
→ wxwxwxwxwxwxwxwx
2
→ wwxxwwxxwwxxwwxx
1
→ wwxwwxwwxwwx
0
→ wwwwwwww
0
Reserved
Must be zero
Table 3 Boot-time Mode Stream
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