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January 20, 2000
1999 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 5901
Advance
Information
x RC4xxx / RC5xxx CPU Bus Interface
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Direct connection between CPU & RC64145
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32- or 64-bit CPU SysAd bus width
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Supports optional external secondary cache controller,
including RC5000
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Bus speeds up to 83MHz
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Big or Little Endian support
x Supports 32- or 64-bit wide CPU bus and 32- or 64-bit
memory
x Memory & Peripheral Controller
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Supports SRAM, Flash ROM, dual-port memory and
peripheral devices
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5 chip selects
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Supports 8-,16-,32- or 64-bit devices
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8-bit boot PROM support
x SDRAM Controller
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32- or 64-bit, up to 4 banks
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Automatic refresh generation
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Address space, up to 512MB
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Stays on page between transfers
x General purpose counter/timers: three 24-bit & one 32-bit
x Interrupt Control
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Allows status of each interrupt to be read and masked
x Programmable IO (PIO)
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Input/Output/Interrupt source
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Individually programmable
x DMA Controller
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4 general purpose DMA channels
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Supports memory-to-memory, memory-to-I/O,memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
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Supports flexible descriptor based operation for scatter/gather
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Supports unaligned transfers
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Supports demand and burst transfers
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Programmable DMA bus transaction burst size, up to 32 bytes
x PCI Bus Interface (Revision 2.1 compatible)
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32-bit PCI, up to 66 MHz
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Target or Master, Host or Satellite
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Plug-and-Play compatible
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Endianess swappers and byte lane data alignment
x UART Interface
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Two 16550 compatible UARTs
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Complete modem support on 1 channel
–
Baud rate support up to 1.5 MBps
x JTAG Interface (IEEE STD.1149.1 compatible)
x 3.3V operation with 5V tolerant inputs
x Available in 388-pin BGA packaging, supports 32- and 64-bit
CPUs