參數(shù)資料
型號(hào): IDT79RC64V145BGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 外設(shè)及接口
英文描述: MULTIFUNCTION PERIPHERAL, PBGA388
封裝: 35 X 35 MM, PLASTIC, BGA-388
文件頁(yè)數(shù): 1/23頁(yè)
文件大?。?/td> 560K
代理商: IDT79RC64V145BGI
1 of 23
January 20, 2000
1999 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 5901
Advance
Information
x RC4xxx / RC5xxx CPU Bus Interface
Direct connection between CPU & RC64145
32- or 64-bit CPU SysAd bus width
Supports optional external secondary cache controller,
including RC5000
Bus speeds up to 83MHz
Big or Little Endian support
x Supports 32- or 64-bit wide CPU bus and 32- or 64-bit
memory
x Memory & Peripheral Controller
Supports SRAM, Flash ROM, dual-port memory and
peripheral devices
5 chip selects
Supports 8-,16-,32- or 64-bit devices
8-bit boot PROM support
x SDRAM Controller
32- or 64-bit, up to 4 banks
Automatic refresh generation
Address space, up to 512MB
Stays on page between transfers
x General purpose counter/timers: three 24-bit & one 32-bit
x Interrupt Control
Allows status of each interrupt to be read and masked
x Programmable IO (PIO)
Input/Output/Interrupt source
Individually programmable
x DMA Controller
4 general purpose DMA channels
Supports memory-to-memory, memory-to-I/O,memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
Supports flexible descriptor based operation for scatter/gather
Supports unaligned transfers
Supports demand and burst transfers
Programmable DMA bus transaction burst size, up to 32 bytes
x PCI Bus Interface (Revision 2.1 compatible)
32-bit PCI, up to 66 MHz
Target or Master, Host or Satellite
Plug-and-Play compatible
Endianess swappers and byte lane data alignment
x UART Interface
Two 16550 compatible UARTs
Complete modem support on 1 channel
Baud rate support up to 1.5 MBps
x JTAG Interface (IEEE STD.1149.1 compatible)
x 3.3V operation with 5V tolerant inputs
x Available in 388-pin BGA packaging, supports 32- and 64-bit
CPUs