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October 14, 1999
1999 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 5607
x High-performance 64-bit embedded Microprocessor
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333MHz operating frequency
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>440 Dhrystone MIPS performance
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666MFLOPS/s floating-point performance
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Up to 125 million multiply accumulate per second (MAC/s)
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MIPS-IV Instruction Set Architecture (ISA), with integer DSP
and 3-operand integer multiply extensions
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Limited dual-issue microarchitecture
x Compatible with RC4640 and RC32364 DSP extensions
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DSP Extensions, for consumer applications
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2-cycle repeat rate, on atomic Multiply-add
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Multiply-subtract (MSUB) support, for complex number
processing
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Count-leading-zero/one support, for string searches and
normalization
x High-performance on-chip cache subsystem
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32kB, two-set associative instruction cache (I-cache)
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32kB, two-set associative data cache (D-cache)
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Write-through and write-back data cache operations
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High-performance cache-ops, bandwidth management
x I-cache and D-cache locking capability (per line), provides
improved real-time support
x Joint TLB on-chip, for virtual-to-physical address mapping
x Big- or Little-endian capability
x RC5000 compatible memory management
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On-chip 48-entry, 96-page TLB, for advanced operating
system support
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Compatible with major operating systems:
WindowsCE, VxWorks, and others
x Bus compatible with IDT 64-bit microprocessor families
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Pipeline runs at 2 to 8 times the bus frequency
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Bus speeds to 125MHz
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32-bit bus option, for lower cost systems
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Enhanced timing protocol for SyncDRAM systems (compatible
with IDT79RC64474/475)
x RC64574:
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32-bit SysAd bus, for low-cost systems
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Pin compatible with RC4640 and RC64474
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128-pin QFP package
x RC64575:
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64-bit SysAd bus interface
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Pin compatible with RC4650 and RC64475
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208-pin QFP package
x JTAG Boundary Scan Interface
x 2.5V operation with 3.3V tolerant I/O