參數(shù)資料
型號(hào): IDT79RC32V364-100DAGI
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 100 MHz, RISC PROCESSOR, PQFP144
封裝: 20 X 20 MM, 1.40 MM HEIGHT, TQFP-144
文件頁(yè)數(shù): 1/21頁(yè)
文件大小: 380K
代理商: IDT79RC32V364-100DAGI
1 of 21
June 20, 2000
2000 Integrated Device Technology, Inc.
*Notice: The information in this document is subject to change without notice
DSC 4510
Block Diagram
The IDT logo is a trademark and ORION, RC4650, RC4640, RV4640, RC4600, RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trademarks of Integrated Device Technology, Inc.
System Control
Coprocessor (CPO)
2kB D-Cache, 2-set,
Clock
En
hanc
ed
JT
AG
(ICE
In
te
rf
ac
e)
TLB
MMU
lockable, write-back/write-through
Generation
Unit
RC32364 Bus Interface Unit
8kB I-Cache,
lockable
2-set,
RISCore32300 Internal Bus Interface
RISCore4000 Compatible
w/
RISCore32300TM
Extended MIPS 32
Integer CPU Core
Features
x
High-performance embedded RISControllerTM
microprocessor, based on IDT RISCore32300TM 32-bit CPU
core
– Based on MIPS 32 RISC architecture with enhancements
– Scalar 5-stage pipeline minimizes branch and load delays
– 66 Million multiply accumulate (MAC) Mul-Add/second
@ 133MHz
– 100 and 133 frequencies
x
MIPS 32 (ISA) instruction set architecture
– MIPS IV compatible conditional move instructions
– MIPS IV superset PREF (prefetch) instruction
– Fast multiplier with atomic multiply-add, multiply-sub
– Count leading zeros/ones instructions
x
Large, efficient on-chip caches
– Separate 8kB Instruction cache and 2kB Data cache
– 2-way set associative
– Write-back and write-through support on a per page basis
– Optional cache locking with “per line” resolution, to facilitate
deterministic response
– Simultaneous instruction and data fetch in each clock cycle,
sustained rate, achieves over 1 GB/sec bandwidth
x
Flexible RC4000 compatible MMU with 32-page TLB on-chip
– Variable page size
– Variable number of locked entries
– No performance penalty for address translation
x
Flexible bus interface allows simple, low-cost designs
– Bus interface runs at a fraction of pipeline rate
– Programmable port-width interface (8-,16-, 32-bit memory and
I/O regions)
– Programmable bus turnaround times (BTA)
– Supports single data or burst transactions
x
Improved real-time support
– Fast interrupt decode
x
Low-power operation
– Active power management: powers down inactive units
– Typical power 700mW @ 133MHz
– Stand-by mode <300mW
x
Enhanced JTAG interface, for low-cost in-circuit emulation
(ICE)
x
MIPS architecture ensures applications software
compatibility throughout the RISController series of
embedded processors
x
Industrial temperature range support
x
3.3V operation (core and I/O)
79RC32364
RISControllerTM Embedded 32-bit
Microprocessor, based on
RISCore32300
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IDT79RC64T574250DZG 64-BIT, 250 MHz, RISC PROCESSOR, PQFP128
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