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參數(shù)資料
| 型號： | IDT79RC32T351-133DHG |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 39/42頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU 32BIT CORE 133MHZ 208-QFP |
| 產(chǎn)品變化通告： | Product Discontinuation 07/Dec/2009 |
| 標準包裝： | 24 |
| 系列： | Interprise™ |
| 處理器類型： | RISC 32-位 |
| 速度： | 133MHz |
| 電壓： | 2.5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 208-BFQFP |
| 供應商設備封裝： | 208-PQFP（28x28） |
| 包裝： | 托盤 |
| 其它名稱： | 79RC32T351-133DHG |
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6 of 42
May 25, 2004
IDT 79RC32351
RWN
O
High Drive Read or Write. This signal indicates if the transaction on the memory and peripheral bus is a read transaction or a write
transaction. A high level indicates a read from an external device, a low level indicates a write to an external device.
OEN
O
High Drive Output Enable. This signal is asserted low when data should be driven by an external device during device read transac-
tions on the memory and peripheral bus.
BWEN[3:0]
O
High Drive SDRAM Byte Enable Mask or Memory and I/O Byte Write Enables. These signals are used as data input/output masks
during SDRAM transactions and as byte write enable signals during device controller transactions on the memory and
peripheral bus. They are active low.
BWEN[0] corresponds to byte lane MDATA[7:0].
BWEN[1] corresponds to byte lane MDATA[15:8].
BWEN[2] corresponds to byte lane MDATA[23:16].
BWEN[3] corresponds to byte lane MDATA[31:24].
SDCSN[1:0]
O
High Drive SDRAM Chip Select. These signals are used to select the SDRAM device on the memory and peripheral bus. Each bit is
asserted low during an access to the selected SDRAM.
RASN
O
High Drive SDRAM Row Address Strobe. The row address strobe asserted low during memory and peripheral bus SDRAM transac-
tions.
CASN
O
High Drive SDRAM Column Address Strobe. The column address strobe asserted low during memory and peripheral bus SDRAM
transactions.
SDWEN
O
High Drive SDRAM Write Enable. Asserted low during memory and peripheral bus SDRAM write transactions.
CKENP
O
Low Drive SDRAM Clock Enable. Asserted high during active SDRAM clock cycles.
Primary function: General Purpose I/O, GPIOP[21].
SDCLKINP
I
STI
SDRAM Clock Input. This clock input is a delayed version of SYSCLKP. SDRAM read data is sampled into the RC32351
on the rising edge of this clock.
ATM Interface
ATMINP[11:0]
I
STI
ATM PHY Inputs. These pins are the inputs for the ATM interface.
ATMIOP[1:0]
I/O
Low Drive
with STI
ATM PHY Bidirectional Signals. These pins are the bidirectional pins for the ATM interface.
ATMOUTP[9:0]
O
Low Drive ATM PHY Outputs. These pins are the outputs for the ATM interface.
TXADDR[1:0]
O
Low Drive ATM Transmit Address [1:0]. 2-bit address bus used for transmission in Utopia-2 mode.
TXADDR[0] Primary function: General purpose I/O, GPIOP[22].
TXADDR[1] Primary function: General purpose I/O, GPIOP[23].
RXADDR[1:0]
O
Low Drive ATM Receive Address [1:0]. 2-bit address bus for receiving in Utopia-2 mode.
RXADDR[0] Primary function: General purpose I/O, GPIOP[24].
RXADDR[1] Primary function: General purpose I/O, GPIOP[25].
General Purpose Input/Output
GPIOP[0]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 serial output, U0SOUTP.
GPIOP[1]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 serial input, U0SINP.
GPIOP[2]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 0 ring indicator, U0RIN.
2nd Alternate function: JTAG boundary scan tap controller reset, JTAG_TRST_N.
GPIOP[3]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
Alternate function: UART channel 0 data carrier detect, U0DCRN.
GPIOP[4]
I/O
Low Drive
with STI
General Purpose I/O. This pin can be configured as a general purpose I/O pin.
1st Alternate function: UART channel 0 data terminal ready, U0DTRN.
2nd Alternate function: CPU or DMA transaction indicator, CPUP.
Name
Type I/O Type
Description
Table 1 Pin Descriptions (Part 2 of 7)
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相關(guān)代理商/技術(shù)參數(shù) |
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| IDT79RC32T355-100DHGI | 制造商:Integrated Device Technology Inc 功能描述:IC MPU 32BIT CORE 100MHZ 208-QFP |
| IDT79RC32T355-133DH | 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32T355-133DHG | 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:Interprise™ 標準包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點:- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應商設備封裝:357-PBGA（25x25） 包裝:托盤 |
| IDT79RC32T355133DHGI | 制造商:IDT 功能描述:Pb Free |
| IDT79RC32T355-133DHGI | 制造商:Integrated Device Technology Inc 功能描述:IC MPU 32BIT CORE 133MHZ 208-QFP |
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