參數(shù)資料
型號: IDT77155L155
廠商: Integrated Device Technology, Inc.
英文描述: PHY (TC-PMD) USER NETWORK INTERFACE FOR 155 MBPS ATM NETWORK APPLICATIONS
中文描述: 物理層(增距鏡TC - PMD)的用戶網(wǎng)絡(luò)接口的155Mbps的ATM網(wǎng)絡(luò)中的應(yīng)用
文件頁數(shù): 34/50頁
文件大?。?/td> 307K
代理商: IDT77155L155
8.03
34
IDT77155
155Mbps ATM PHY (TC-PMD) USER NETWORK INTERFACE
ADVANCED INFORMATION
Commercial Temperature Range
RECEIVE CELL MATCH HEADER REGISTER
ADDRESS 0X52
DEFAULT = 8’B00000000
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
GFC[3]
GFC[2]
GFC[1]
GFC[0]
PTI[2]
PTI[1]
PTI[0]
CLP
Function
GFC Bit 3 to match GFC of receive header
GFC Bit 2 to match GFC of receive header
GFC Bit 1 to match GFC of receive header
GFC Bit 0 to match GFC of receive header
PTI Bit 2 to match PTI of receive header
PTI Bit 1 to match PTI of receive header
PTI Bit 0 to match PTI of receive header
CLP value to match CLP of receive header
NOTE:
1. GFC[3:0], PTI[2:0], CLPMatch header pattern to match in the GFC, PTI, & CLP portion of the received header. Cells matching the unmasked bits of this
pattern, along with the criteria of VPI = VCI = 0, will be dropped. The receive pass bit control must be disabled to enable the dropping of idle/unassigned
cells.
RECEIVE CELL MATCH HEADER MASK REGISTER
ADDRESS 0X53
DEFAULT = 8’B00000000
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Symbol
GFCmsk[3]
GFCmsk[2]
GFCmsk[1]
GFCmsk[0]
PTImsk[2]
PTImsk[1]
PTImsk[0]
CLPmsk
Function
Mask GFC Bit 3
Mask GFC Bit 2
Mask GFC Bit 1
Mask GFC Bit 0
Mask PTI Bit 2
Mask PTI Bit 1
Mask PTI Bit 0
Mask CLP
NOTE:
1. GFCmsk[3:0], PTImsk[2:0], CLPmsk Mask bits for GFC, PTI, & CLP portion of the match header pattern. Cells matching the unmasked bits of the header
pattern register (‘h52) will be dropped. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. Note that the
VPI and VCI bits do not have a mask register. The pattern in them have to be a logic zero.
RECEIVE CELL CORRECTABLE ERROR COUNTER
ADDRESS 0X54
DEFAULT = 8’BXXXXXXXX
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R
R
R
R
R
R
R
R
Symbol
corCnt[7]
corCnt[6]
corCnt[5]
corCnt[4]
corCnt[3]
corCnt[2]
corCnt[1]
corCnt[0]
Function
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
Correctable HEC error count bit
NOTE:
1. corCnt [7:0] Correctable HEC error count register. This is a cumulative error counter keeping track of errors from the previous poll of these registers. The
error count is polled by writing to either of the HEC error registers (‘h54 or ‘h55), or to address ‘h00. Such a write transfers accumulated errors to a holding
register which may be read later, and the registers are cleared. This transfer and reset of the registers are done such that coincident events are not lost.
All error registers in the receive sections of the transmission convergence block or the cell delineation block may be polled by a write to the master register
‘h00.
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