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參數(shù)資料
| 型號： | IDT77010 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Data Path Interface to Utopia Level 1 Translation Device |
| 中文描述： | 數(shù)據(jù)通道接口的烏托邦1級轉換設備 |
| 文件頁數(shù)： | 8/21頁 |
| 文件大?。?/td> | 141K |
| 代理商： | IDT77010 |
8 of 21
June 24, 2002
IDT77010
Input Control Cell Formatting
Control cells are generatedby a remote computerandare usedto
configureandmonitorthePHY registers.AllcellshavingtheheaderVPI
= 0x00 hex and VCI = 0x1F hex (VCI bits 11-4) are decoded and
executedascontrolcellsbythe77010.
Control Cell Filter Operation
All cells transferredoverthe DTxDATA[3:0] bus are testedtosee if
theyarecontrolcells.CellscontainingtheheaderVPI=00HexandVCI
=1F Hex(VCIbits11-4)arefilteredascontrolcellsandnotforwardedto
theTxDATA[7:0]bus. Thefilterignores theGFC, PTIandCLP bits. The
defaultcontrol cellidentifiervalue is 00x1F. Itcanbeprogrammedtoa
userdefinedvalueviatheChangeControlCellAddressCommand(see
page16).
Control Cell Frequency
Thecontrolcells arrivemultiplexedwithdatacells inrandomcombi-
nations, andaretermnated(filtered) bythe77010.
TheRxDATA[3:0]bus multiplexes thereceiveUTOPIAcells andany
internallygeneratedcontrolcells.Thecontrolcellisignoredifaprevious
control cell is being executed at that time. A gap in the UTOPIA cell
streammustoccurbeforethenewcontrolcellisprocessed,becausethe
UTOPIAreceivecellshavehigherpriority.
Control cells may be input back-to-back. However, the second
controlcellwillnotbeprocessedandcouldbedropped,eventhoughthe
77010canfilterbothofthemWorstcaseconditioniswhenthereceive
UTOPIA bus is at full rate. In this case it is recommended that the
controlcellsbeatleast50cellsapart.
DPI Interfac e Operation
DataPathInterface(DPI) isasynchronousbusinterfacedesignedto
transfer ATMcells between two devices. The 77010 contains a DPI-4
bus interface, whichcontains a four bit wide data bus. Therefore, 107
clockcyclesarerequiredtotransfera53byteATMcell.
The77010has separateDPI-4transmtandreceiveinterfaces, with
eachrequiringsixsignals. Thesignalsareaclock, astartofcellmarker
anda four bit data bus. All signals are sampled on the rising edge of
theirrespectiveclock.
Transmit DPI Bus Interfac e
TheTransmtDPIClock(DTxCLK)isgeneratedfromSYSCLKandis
twicethefrequencyofTCLK.Thisclockisnotcontinuousandisusedto
control data flow to the PHY device. DTxCLK is initially low and not
drivenuntil the 77010 detects a highTCLAV fromthe PHY device. On
the rising edge of DTxCLK the 77010 samples Transmt Start of Cell
(DTxFRM), which is generated by the transmtting device for one
DTxCLK cycle. WhenDTxFRMis assertedhighthe 77010 will sample
valid data (DTxDATA[3:0]) on the next rising edge of DTxCLK. Cell
transferwillcontinuewithoutinterruptiononceithasstarted.
WhenTCLAV is de-assertedlowthe current cell is transferredand
DTxCLK goeslowuntilanotherhighTCLAV isdetected.
DTxFRM and DTxDATA[3:0] are sampled on the rising edge of
DTxCLK.
Control AT M Cell Format
Cell Byte
Number
Bit
Number
Func tion
Name
Bit
Contents
Desc ription
0
7-4
GFC
0xX
Don'tcare.
0
3-0
VPI7-4
0x0
Mustbesetto0x0.
1
7-4
VPI3-0
0x0
Mustbesetto0x0.
1
3-0
VCI15-12
0x0
Mustbesetto0x0.
2
7-0
VCI11-4
0xYY
SpecialVCIvalueforcontrolandstatuscells.Defaultis0x1F.
1
3
7-4
VCI3-0
0x0
Don'tcare.
3
3-1
PTI
000'b
Don'tcare.
3
0
CLP
0'b
Don'tcare.
4
7-0
HEC
0x00
Don'tcare.
5
7-0
Command
00-FF Hex
Commandcellbyte.
6
7-0
DataA
0x0-0xFF
Parameterforcontrolcell.
7
7-0
DataB
0x0-0xFF
Parameterforcontrolcell.
8
7-0
reserved
0x00
Alwayssetto0x00.
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