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參數(shù)資料
| 型號： | IDT74SSTVN16859PAG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 6/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUFFER 13-26BIT SSTL 64-TSSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 09/Dec/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 邏輯類型： | 13 位至 26 位寄存緩沖器，帶 SSTL_2 輸入和輸出 |
| 電源電壓： | 2.3 V ~ 2.7 V |
| 位數(shù)： | 13，26 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-TFSOP （0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 64-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74SSTVN16859PAG8 |
6
COMMERCIALTEMPERATURERANGE
IDT74SSTVN16859
13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O
TEST CIRCUITS AND WAVEFORMS
FOR PC1600 - PC2700, VDD = 2.5V ± 0.2V
FOR PC3200, VDD = 2.6V ± 0.1V
Voltage Waveforms - Pulse Duration
NOTES:
1. CL includes probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and IO = 0mA.
3. All input pulses are supplied by generators having the following characteristics: PRR
≤10MHz, ZO = 50Ω, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VTT = VREF = VDDQ/2
6. VIH = VREF + 310mV (AC voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 310mV (AC voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. tPDM is tPD with one output switching. tPDMSS is tPD with all outputs switching.
Load Circuit
Voltage Waveforms - Setup and Hold Times
Voltage Waveforms - Propagation Delay Times
Voltage and Current Waveforms
Inputs Active and Inactive Times
Timing
Input
VICR
VI(PP)
tPLH
tPHL
Output
VOH
VOL
VICR
VTT
VOH
VOL
VIH
VIL
tPHL
VDD/2
VTT
LVCMOS
RESET
Input
Output
VREF
VIH
VIL
VREF
Input
tW
VREF
VIH
VIL
VREF
Input
VICR
VI(PP)
tSU
tH
Timing
Input
RL =50
Ω
CL =30 pF
(see note 1)
Test Point
LVCMOS
RESET
Input
VDD/2
VDD
tINACT
tACT
IDD
VDD/2
90%
0V
(see note 2)
10%
VTT
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