參數(shù)資料
型號: IDT74SSTVF16857PAG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大?。?/td> 0K
描述: IC BUFFER 14BIT SSTL I/O 48-TSSO
標(biāo)準(zhǔn)包裝: 2,000
系列: 74SSTVF
邏輯類型: 寄存緩沖器,帶 SSTL_2 輸入和輸出
電源電壓: 2.3 V ~ 2.7 V
位數(shù): 14
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 48-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 48-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74SSTVF16857PAG8
1
COMMERCIALTEMPERATURERANGE
IDT74SSTVF16857
14-BIT REGISTERED BUFFER WITH SSTL I/O
JUNE 2003
2003 Integrated Device Technology, Inc.
DSC-6198/8
c
IDT74SSTVF16857
COMMERCIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
14-BIT REGISTERED
BUFFER WITH SSTL I/O
DESCRIPTION:
The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V
VDD and supports low standby operation. All data inputs and outputs are
SSTL_2 level compatible with JEDEC standard for SSTL_2.
RESET is an LVCMOS input since it must operate predictably during the
power-up phase. RESET, which can be operated independent of CLK and
CLK, must be held in the low state during power-up in order to ensure
predictable outputs (low state) before a stable clock has been applied.
RESET, when in the low state, will disable all input receivers, reset all
registers,andforcealloutputstoalowstate,beforeastableclockhasbeen
applied. Withinputsheldlowandastableclockapplied,outputswillremain
low during the Low-to-High transition of RESET.
FEATURES:
2.3V to 2.7V Operation
SSTL_2 Class I style data inputs/outputs
Differential CLK input
RESET control compatible with LVCMOS levels
Flow-through architecture for optimum PCB design
Drive up to equivalent of 14 SDRAM loads
Latch-up performance exceeds 100mA
ESD >2000V per MIL-STD-883, Method 3015; >200V using
machine model (C = 200pF, R = 0)
Available in TSSOP package
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
APPLICATIONS:
Along with CSPT857C, Zero Delay PLL Clock buffer, provides
complete solution for DDR1 DIMMs
34
38
39
35
48
R
1D
C1
1
Q1
RESET
CLK
VREF
D1
TO 13 OTHER CHANNELS
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