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參數(shù)資料
| 型號(hào)： | IDT74LVCH32374ABF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, QUAD 8-BIT DRIVER, TRUE OUTPUT, PBGA96 |
| 封裝： | LFBGA-96 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 117K |
| 代理商： | IDT74LVCH32374ABF |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH32374A
3.3VCMOS32-BITEDGE-TRIGGEREDD-TYPEFLIP-FLOP
1
FEBRUARY 2000
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2000 Integrated Device Technology, Inc.
DSC-4768/1
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in 96-ball LFBGA package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
Balanced Output Drivers: ±24mA
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVCH32374A
DESCRIPTION:
The LVCH32374A 32-bit edge-triggered D-type flip-flop is built using
advanced dual metal CMOS technology. This high-speed, low-power
register is ideal for use as a buffer register for data synchronization and
storage. The Output Enable (OE) and clock (CLK) controls are organized
to operate the device as four 8-bit registers, two 16-bit registers, or one 32-
bit register with common clock. Flow-through organization of signal pins
simplifies layout. All inputs are designed with hysteresis for improved noise
margin.
All pins of the LVCH32374A can be driven from either 3.3V or 5V devices.
This feature allows the use of this device as a translator in a mixed 3.3V/
5V supply system.
The LVCH32374A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH32374A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 32-BIT
EDGE-TRIGGERED D-TYPE
FLIP-FLOP WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O, BUS-HOLD
2
OE
D
C
2
CLK
2
D1
2
Q1
TO SEVEN OTHER CHANNELS
H3
H4
E5
E2
4
OE
D
C
4
CLK
4
D1
4
Q1
TO SEVEN OTHER CHANNELS
T3
T4
N5
N2
1
OE
D
C
1
CLK
D1
1
Q1
TO SEVEN OTHER CHANNELS
3
OE
D
C
3
CLK
3
D1
3
Q1
TO SEVEN OTHER CHANNELS
J3
J4
J5
J2
A3
A4
A5
A2
D
C
D
C
D
C
D
C
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