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參數(shù)資料
| 型號： | IDT74LVCH16646APFG8 |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC BUS TRSCVR 3-ST 16BIT 56TVSOP |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 系列： | 74LVCH |
| 邏輯類型： | 寄存收發(fā)器，非反相 |
| 元件數(shù)： | 2 |
| 每個(gè)元件的位元數(shù)： | 8 |
| 輸出電流高，低： | 24mA，24mA |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TVSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 74LVCH16646APFG8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVCH16646A
3.3V CMOS 16-BIT BUS TRANSCEIVER/REGISTER
1
JUNE 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-3787/4
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μμμμμ W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in TSSOP and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVCH16646A
DESCRIPTION:
The LVCH16646A 16-bit bus transceiver and register is built using
advanced dual metal CMOS technology. This high-speed, low power
device is organized as two independent 8-bit D-type transceivers with 3-
state D-type registers.The controls circuitry is organized for multiplexed
transmission of data between A bus and B bus either directly or from the
internal storage registers. Each 8-bit transceiver/register features direction
control (DIR), over-riding Output Enable control (
OE) and Select lines (SAB
and SBA) to select either real- time data or stored data. Separate clock inputs
are provided for A and B port registers. Data on the A or B data bus, or both,
can be stored in the internal registers by the low-to-high transitions at the
appropriate clock pins. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved noise margin.
All pins can be driven from either 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mixed 3.3V/5V supply system.
The LVCH16646A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16646A has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
3.3V CMOS 16-BIT BUS
TRANSCEIVER/REGISTER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
TO SEVEN OTHER CHANNELS
1
B1
1D
C1
1D
C1
1
A1
1
SAB
1
CLKAB
1
SBA
1OE
1
CLKBA
2
B1
1D
C1
1D
C1
2
A1
2
SAB
2
CLKAB
2
SBA
2
OE
2
CLKBA
2
DIR
1
DIR
56
1
55
54
2
3
5
29
28
30
31
27
26
15
52
42
One of Eight Channels
TO SEVEN OTHER CHANNELS
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