參數(shù)資料
型號: IDT74LVCH16245APA
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 通用總線功能
英文描述: 3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS, 5 VOLT TOLERANT I/O AND BUS-HOLD
中文描述: LVC/LCX/Z SERIES, DUAL 8-BIT TRANSCEIVER, TRUE OUTPUT, PDSO48
封裝: TSSOP-48
文件頁數(shù): 1/6頁
文件大小: 91K
代理商: IDT74LVCH16245APA
INDUSTRIAL TEMPERATURE RANGE
IDT74LVCH16245A
3.3V CMOS 16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS
1
MARCH 1999
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4596/1
FEATURES:
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μ
W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIV E FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVCH16245A
DESCRIPTION:
This 16-bit bus transceiver is built using advanced dual metal CMOS
technology. This high-speed, low power transceiver is ideal for asynchro-
nous communication between two busses (A and B). The Direction and
Output Enable controls are designed to operate this device as either two
independent 8-bit transceivers or one 16-bit transceiver. The direction
control pin (DIR) controls the direction of data flow. The output enable pin
(
OE
) overrides the direction control and disables both ports. All inputs are
designed with hysteresis for improved noise margin.
All pins can be driven fromeither 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mxed 3.3V/5V supply system
The LVCH16245A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The LVCH16245A has “bus-hold” which retains the inputs' last state
whenever the input goes to a high impedance. This prevents floating inputs
and elimnates the need for pull-up/down resistors.
3.3V CMOS 16-BIT
BUS TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O AND BUS-HOLD
1
DIR
1
A
1
1
A
2
1
A
3
1
A
4
1
A
5
1
A
6
1
A
7
1
A
8
1
B
8
1
B
7
1
B
6
1
B
5
1
B
4
1
B
3
1
B
2
1
B
1
1
OE
2
DIR
2
A
1
2
A
2
2
A
3
2
A
4
2
A
5
2
A
6
2
A
7
2
A
8
2
B
8
2
B
7
2
B
6
2
B
5
2
B
4
2
B
3
2
B
2
2
B
1
2
OE
1
47
46
44
43
41
40
38
37
48
2
3
5
6
8
9
11
12
24
36
35
33
32
30
29
27
26
25
13
14
16
17
19
20
22
23
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