參數(shù)資料
型號: IDT74LVC16601APVG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/6頁
文件大?。?/td> 0K
描述: IC UNIV BUS TXRX 18BIT 56SSOP
標(biāo)準(zhǔn)包裝: 1,000
系列: 74LVC
邏輯類型: 通用總線收發(fā)器,CMOS
電路數(shù): 18 位
輸出電流高,低: 24mA,24mA
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 帶卷 (TR)
其它名稱: 74LVC16601APVG8
INDUSTRIALTEMPERATURERANGE
2
IDT74LVC16601A
3.3VCMOS18-BIT UNIVERSAL BUS TRANSCEIVER
SSOP/ TSSOP
TOP VIEW
PIN CONFIGURATION
Symbol
Description
Max
Unit
VTERM
Terminal Voltage with Respect to GND
–0.5 to +6.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–50 to +50
mA
IIK
Continuous Clamp Current,
–50
mA
IOK
VI < 0 or VO < 0
ICC
Continuous Current through each
±100
mA
ISS
VCC or GND
ABSOLUTE MAXIMUM RATINGS(1)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. As applicable to the device type.
Symbol
Parameter
(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
4.5
6
pF
COUT
Output Capacitance
VOUT = 0V
6.5
8
pF
CI/O
I/O Port Capacitance
VIN = 0V
6.5
8
pF
CAPACITANCE (TA = +25°C, F = 1.0MHz)
OEAB
A1
GND
A2
A3
VCC
A4
A5
GND
A6
A7
A8
A9
A11
A12
GND
A13
A14
A15
VCC
A16
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
48
49
50
51
52
53
54
55
56
1
CLKENAB
B1
GND
B2
B3
VCC
B4
B5
B6
B7
B8
B9
GND
B11
B12
B13
B14
GND
B15
B16
B17
GND
A18
OEBA
LEBA
25
26
27
28
32
31
30
29
GND
B18
CLKBA
CLKENBA
A10
A17
VCC
B10
LEAB
CLKAB
NOTES:
1. H = HIGH Voltage Level
X = Don’t Care
L = LOW Voltage Level
Z = High-Impedance
↑ = LOW-to-HIGH transition
2. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA, CLKBA,
and
CLKENBA.
3. Output level before the indicated steady-state input conditions were established.
4. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
Inputs
Outputs
CLKENAB
OEAB
LEAB
CLKAB
Ax
Bx
XH
X
Z
XL
H
X
L
XL
H
X
H
HL
L
X
B(3)
LL
L
LL
L
HH
LL
L
X
B(3)
LL
L
H
X
B(4)
FUNCTION TABLE(1,2)
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
CLKENAB
A-to-B Clock Enable Input (Active LOW)
CLKENBA
B-to-A Clock Enable Input (Active LOW)
PIN DESCRIPTION
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