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參數(shù)資料
| 型號： | IDT74LVC16543APV8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | LVC/LCX/Z SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.635 MM PITCH, SSOP-56 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大小： | 81K |
| 代理商： | IDT74LVC16543APV8 |
INDUSTRIALTEMPERATURERANGE
IDT74LVC16543A
3.3VCMOS16-BIT REGISTERED TRANSCEIVER
1
JULY 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4730/2
FEATURES:
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
W typ. static)
All inputs, outputs, and I/O are 5V tolerant
Supports hot insertion
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
IDT74LVC16543A
3.3V CMOS 16-BIT
REGISTERED TRANSCEIVER
WITH 3-STATE OUTPUTS,
5 VOLT TOLERANT I/O
DESCRIPTION:
The LVC16543A 16-bit registered transceiver is built using advanced
dual metal CMOS technology. This high-speed, low-power device can be
used as two 8-bit transceivers or one 16-bit transceiver. Separate latch-
enable (LEAB or LEBA) and output-enable (OEAB or OEBA) inputs are
provided for each register to permit independent control in either direction
of data flow. For example, the A-to-B enable (CEAB) must be low to enter
data from the A port or to output data from the B port. LEAB controls the
latch function. When LEAB is low, the latches are transparent. A subse-
quent low-to-high transition of LEAB signal puts the Alatches in the storage
mode. OEAB performs the output enable function on the B port. Data flow
from the B port to the A port is similar but requires using CEBA, LEBA, and
OEBA inputs. Flow-through organization of signal pins simplifies layout. All
inputs are designed with hysteresis for improved noise margin.
All pins of this 16-bit latched transceiver can be driven from either 3.3V
or 5V devices. This feature allows the use of this device as a translator in
a mixed 3.3V/5V supply system.
The LVC16543A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
C1
1D
1
B1
1
LEAB
1
CEAB
1
OEAB
1
LEBA
1
CEBA
1
OEBA
TO SEVEN OTHER CHANNELS
1
A1
2
B1
2
LEAB
2
CEAB
2
OEAB
2
LEBA
2
CEBA
2
OEBA
TO SEVEN OTHER CHANNELS
2
A1
56
54
55
1
3
2
5
29
31
30
28
26
27
15
42
52
C1
1D
C1
1D
C1
1D
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| IDT74LVC16601APAG | 功能描述:IC UNIV BUS TXRX 18BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74LVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74LVC16601APAG8 | 功能描述:IC UNIV BUS TXRX 18BIT 56TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74LVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
| IDT74LVC16601APVG | 功能描述:IC UNIV BUS TXRX 18BIT 56SSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 通用總線函數(shù) 系列:74LVC 產(chǎn)品變化通告:Product Discontinuation 09/Dec/2010 標(biāo)準(zhǔn)包裝:1,500 系列:74AVC 邏輯類型:通用總線驅(qū)動器 輸入數(shù):- 電路數(shù):18 位 輸出電流高，低:12mA，12mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:56-TFSOP（0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:56-TSSOP 包裝:帶卷 (TR) |
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| IDT74LVC16823APA | 制造商:Integrated Device Technology Inc 功能描述:Flip Flop, 18-BIT, D Type, 56 Pin, Plastic, TSSOP |
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