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參數(shù)資料
| 型號： | IDT74LVC138A |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER WITH 5 VOLT TOLERANT I/O |
| 中文描述： | 3.3V的CMOS三線，8線譯碼器/分路器與5伏的I / O |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 89K |
| 代理商： | IDT74LVC138A |
INDUSTRIAL TEMPERATURE RANGE
IDT74LVC138A
3.3V CMOS 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
1
AUGUS T 1999
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4722/1
FEATURES:
0.5 MICRON CMOS Technology
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
CMOS power levels (0.4
μ
W typ. static)
Rail-to-Rail output swing for increased noise margin
All inputs, outputs, and I/Os are 5V tolerant
Supports hot insertion
Available in QSOP, SOIC, SSOP, and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
DRIV E FEATURES:
High Output Drivers: ±24mA
Reduced system switching noise
APPLICATIONS:
5V and 3.3V mixed voltage systems
Data communication and telecommunication systems
IDT74LVC138A
DESCRIPTION:
The LVC138A 3-line to 8-line decoder/demultiplexer is built using
advanced dual metal CMOS technology. This device is designed for high-
performance memory-decoding or data-routing applications requiring very
short propagation delay times. In high performance memory systems, this
decoder mnimzes the effects of systemdecoding. When employed with
high-speed memories utilizing a fast enable circuit, the delay times of these
decoders and the enable time of the memory are usually less than the typical
access time of the memory. This means that the effective systemdelay
introduced by the decoder is negligible.
The conditions at the binary-select inputs and the three enable inputs
select one of eight output lines. Two active-low enable inputs and one active-
high enable input reduce the need for external gates or inverters when
expanding. A 24-line decoder can be implemented without external invert-
ers and a 32-line decoder requires only one inverter. An enable input can
be used as a data input for demultiplexing applications.
Inputs can be driven fromeither 3.3V or 5V devices. This feature allows
the use of this device as a translator in a mxed 3.3V/5V supply system
The LVC138A has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
3.3V CMOS
3-LINE TO 8-LINE
DECODER/DEMULTIPLEXER
WITH 5 VOLT TOLERANT I/O
Y0
15
G1
Y1
14
Y2
13
Y3
12
A
1
2
3
B
Select
Inputs
Data
Outputs
Enable
Inputs
G2A
G2B
6
4
5
C
Y4
11
Y5
10
Y6
9
Y7
7
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74LVC138ADC | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APA | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74LVC162244APAG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:2,000 系列:74LVCH 邏輯類型:緩沖器/線路驅(qū)動器，非反相 元件數(shù):2 每個元件的位元數(shù):4 輸出電流高，低:24mA，24mA 電源電壓:1.65 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:20-SOIC 包裝:帶卷 (TR) |
| IDT74LVC162244APAG8 | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動器，非反相 元件數(shù):4 每個元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 |
| IDT74LVC162244APFG | 功能描述:IC BUFF DVR TRI-ST 16BIT 48TVSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 緩沖器，驅(qū)動器，接收器，收發(fā)器 系列:74LVC 標(biāo)準(zhǔn)包裝:47 系列:74LVX 邏輯類型:緩沖器/線路驅(qū)動器，非反相 元件數(shù):4 每個元件的位元數(shù):1 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:14-SOIC（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:14-SOIC 包裝:管件 |
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