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參數(shù)資料
| 型號(hào)： | IDT74GTLP16612PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 總線收發(fā)器 |
| 英文描述： | GTLP SERIES, 18-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | TSSOP-56 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 72K |
| 代理商： | IDT74GTLP16612PA8 |
1
IDT74GTLP16612
CMOS 18-BIT TTL/GTLP UNIVERSAL BUS TRANSCEIVER
INDUSTRIALTEMPERATURERANGE
OCTOBER 1999
1999
Integrated Device Technology, Inc.
DSC-5477/3
c
IDT74GTLP16612
INDUSTRIAL TEMPERATURE RANGE
CMOS 18-BIT TTL/GTLP
UNIVERSAL BUS
TRANSCEIVER
DESCRIPTION:
The GTLP16612 is an 18-bit universal bus transceiver. It provides
signal level translation, from TTL to GTLP, for applications requiring a high-
speed interface between cards operating at TTL logic levels and back-
planes operating at GTLP logic levels. GTLP provides reduced output
swing (<1V), reduced input threshold levels, and output edge-rate control
to minimize signal setting times. The GTLP16612 is a derivative of the Gun-
ning Transceiver Logic (GTL) JEDEC standard JESD8-3 and incorporates
internal edge-rate control, which is process, voltage, and temperature
(PVT) compensated.
GTLP output low voltage is less than 0.5V. The output high is 1.5V, and
the receiver threshold is 1V.
CE
CLK
GTLP
C1
1D
CE
CLK
C1
1D
ONE OF 18 CHANNELS
TO 17 OTHER CHANNELS
OEAB
CEAB
CLKAB
LEAB
LEBA
CLKBA
CEBA
OEBA
A1
54
B1
1
56
55
2
28
30
29
27
3
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Bidirectional interface between GTLP and TTL logic levels
Edge Rate Control Circuit reduces output noise
VREF pin provides reference voltage for receiver threshold
CMOS technology for low power dissipation
Special PVT Compensation circuitry to provide consistent perfor-
mance over variations of process, supply voltage, and temperature
5V tolerant inputs and outputs on A-Port
Bus-Hold to eliminate the need for external pull-up resistors for
unused inputs to A-Port
Power up/down high-impedance
TTL-compatible Driver and Control inputs
High Output source/sink ±32mA on A-Port pins
Flow-through architecture optimizes system layout
D-type latch and flip-flop architecture for data flow in clocked,
transparent, or latched mode
Open drain on GTLP to support wired OR connection
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
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