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參數(shù)資料
| 型號(hào)： | IDT74FST1632861PV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | 20-BIT, TWO PORT BUS SWITCH WITH RESISTOR |
| 中文描述： | CBT/FST/QS/5C/B SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO48 |
| 封裝： | SSOP-48 |
| 文件頁(yè)數(shù)： | 5/6頁(yè) |
| 文件大?。?/td> | 87K |
| 代理商： | IDT74FST1632861PV |
5
INDUSTRIAL TEMPERATURE RANGE
IDT74FST1632861
20-BIT, TWO PORT BUS SWITCH WITH RESISTOR
D.U.T.
V
CC
1 MHz
Signal
Generator
C
L
=
50pF
(3)
V
OUT
Switch
Out
Enable/Select
Switch In
Switch In (MUX)
(1)
(2)
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
Ω
500
Ω
7.0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
DATA
INPUT
TIMING
INPUT
ASYNCHRONOUS
CONTROL
SYNCHRONOUS
CONTROL
t
SU
t
H
t
REM
t
SU
t
H
HIGH-LOW-HIGH
PULSE
LOW-HIGH-LOW
PULSE
t
W
1.5V
1.5V
SAME PHASE
INPUT TRANSITION
3V
1.5V
0V
V
OH
1.5V
V
OL
t
PLH
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
3V
1.5V
0V
t
PLH
t
PHL
t
PHL
CONTROL
INPUT
3V
1.5V
0V
3.5V
0V
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
V
OL
0.3V
0.3V
t
PLZ
t
PZL
t
PHZ
3.5V
1.5V
0V
1.5V
ENABLE
DISABLE
V
OH
TEST CIRCUITS AND WAV EFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
Set-up, Hold, and Release Times
Pulse Width
NOTES:
1. Diagramshown for input Control Enable-LOW and input Control Disable-HIGH.
2. Pulse Generator for All Pulses: Rate
≤
1.0MHz; t
F
≤
2.5ns; t
R
≤
2.5ns.
Test
Switch
Open Drain
Disable Low
Enable Low
All Other Tests
Closed
Open
SWITCH POSITION
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termnation resistance: should be equal to Z
OUT
of the Pulse Generator.
Charge Injection
NOTES:
1. Select is used with multiplexers for measuring IQ
DCI
I during multiplexer select. During
all other tests Enable is used.
2. Used with multiplexers to measure IQ
DCI
I only.
3. Charge Injection =
Δ
V
OUT
C
L
, with Enable toggling for IQ
CI
I or Select toggling for IQ
DCI
I.
Δ
V
OUT
is the change in V
OUT
and is measured with a 10M
Ω
probe.
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