參數(shù)資料
型號(hào)： IDT74FCT823CTQG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 通用總線功能
英文描述： HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
中文描述： FCT SERIES, 9-BIT DRIVER, TRUE OUTPUT, PDSO24
封裝： GREEN, QSOP-24
文件頁(yè)數(shù)： 2/7頁(yè)
文件大?。?/td> 88K
代理商： IDT74FCT823CTQG
INDUSTRIAL TEMPERATURE RANGE
2
IDT74FCT823AT/CT
HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTER
PIN CONFIGURATION
Symbol
V
TERM
(2)
V
TERM
(3)
T
STG
I
OUT
Description
Max
Unit
V
V
°C
mA
Termnal Voltage with Respect to GND
Termnal Voltage with Respect to GND
Storage Temperature
DC Output Current
–0.5 to +7
–0.5 to V
CC
+0.5
–65 to +150
–60 to +120
ABSOLUTE MAX IMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability. No termnal voltage may exceed
Vcc by +0.5V unless otherwise noted.
2. Inputs and Vcc termnals only.
3. Output and I/O termnals only.
Symbol
C
IN
C
OUT
Parameter
(1)
Input Capacitance
Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Typ.
6
8
Max.
10
12
Unit
pF
pF
CAPACITANCE
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested.
FUNCTION TABLE
(1)
Internal/
Outputs
Qx
L
H
L
L
NC
NC
L
H
L
H
Inputs
EN
L
L
X
X
H
H
L
L
L
L
OE
H
H
H
L
H
L
H
H
L
L
CLR
H
H
L
L
H
H
H
H
H
H
Dx
L
H
X
X
X
X
L
H
L
H
CP
↑
↑
X
X
X
X
↑
↑
↑
↑
Yx
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High Z
Clear
Hold
Load
NOTE:
1. H = HIGH Voltage Level
X = Dont Care
L = LOW Voltage Level
NC = No Change
↑
= LOW-to-HIGH Transition
Z = High Impedance
2
3
1
20
19
18
15
16
9
10
D
6
D
7
D
2
D
5
D
3
D
4
D
8
23
22
24
21
17
5
6
7
4
8
D
0
V
CC
CP
OE
13
14
11
12
D
1
GND
CLR
Y
6
Y
7
Y
2
Y
5
Y
3
Y
4
Y
8
Y
0
Y
1
EN
SOIC/ QSOP
TOP VIEW
Pin Names
Dx
CLR
I/O
I
I
Description
D Flip-Flop Data Inputs
When the clear input is LOW and
OE
is LOW, the
Qx outputs are LOW. When the clear input is HIGH,
data can be entered into the register.
Clock Pulse for the Register; enters data into the
register on the LOW-to-HIGH transition.
Register 3-State Outputs
Clock Enable. When the clock enable is LOW, data
on the Dx output is transferred to the Qx output on the
LOW-to-HIGH transition. When the clock enable is
HIGH, the Qx outputs do not change state, regardless
of the data or clock input transitions.
Output Control. When the
OE
is HIGH, the Yx
outputs are in the high-impedance state. When the
OE
is LOW, the TRUE register data is present at the
Yx outputs.
CP
I
Yx
EN
O
I
OE
I
PIN DESCRIPTION
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