參數(shù)資料
型號: IDT74FCT646CTQ8
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 總線收發(fā)器
英文描述: FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24
封裝: QSOP-24
文件頁數(shù): 1/8頁
文件大小: 96K
代理商: IDT74FCT646CTQ8
INDUSTRIALTEMPERATURERANGE
IDT74FCT646AT/CT
FASTCMOSOCTALTRANSCEIVER/REGISTER(3-STATE)
1
FEBRUARY 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-5505/6
FEATURES:
A and C grades
Low input and output leakage
≤≤≤≤≤1A (max.)
CMOS power levels
True TTL input and output compatibility:
–VOH = 3.3V (typ.)
–VOL = 0.3V (typ.)
High Drive outputs (-15mA IOH, 64mA IOL)
Meets or exceeds JEDEC standard 18 specifications
Power off disable outputs permit "live insertion"
Available in SOIC, SSOP, and QSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT646AT/CT
FAST CMOS OCTAL
TRANSCEIVER/
REGISTER (3-STATE)
DESCRIPTION:
The FCT646T consists of a bus transceiver with 3-state D-type flip-flops
and control circuitry arranged for multiplexed transmission of data directly
from the data bus or from the internal storage registers. The FCT646T
utilizes the enable control (
G) and direction (DIR) pins to control the
transceiver functions.
SAB and SBA control pins are provided to select either real- time or stored
data transfer. The circuitry used for select control will eliminate the typical
decoding glitch that occurs in a multiplexer during the transition between
stored and real-time data. A low input level selects real-time data and a high
selects stored data.
Data on the A or B data bus, or both, can be stored in the internal D flip-
flops by low-to-high transitions at the appropriate clock pins (CPAB or
CPBA), regardless of the select or enable control pins.
A1
G
DIR
CPB A
SB A
CPA B
SA B
ONE OF EIGH T CHANNELS
B REG
A REG
B1
1D
C1
1D
TO SEVEN OTHE R CHANN ELS
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