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參數(shù)資料
| 型號： | IDT74FCT3932-100PA |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER |
| 中文描述： | 3.3V的低歪曲基于PLL的CMOS時鐘驅(qū)動器 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 131K |
| 代理商： | IDT74FCT3932-100PA |
IDT74FCT3932-100, IDT74FCT32932-100
LOW SKEW PLL-BASED CLOCK DRIVER
COMMERCIAL TEMPERATURE RANGES
IDT74FCT32932-100
ADVANCE INFORMATION
9.9
Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
NOVEMBER 1996
1996 Integrated Device Technology, Inc.
9.9
DSC-3267/2
FEATURES:
0.5 MICRON CMOS Technology
Guaranteed low skew
16 programmable frequency configurations
17 3-state outputs:
±
24 mA FCT3932
±
8 mA FCT32932
Output configuration:
BANK1: 4 outputs
BANK2: 8 outputs
BANK3: 5 outputs
Dedicated feedback output (Q_FB)
Maximum output frequency:
V
CC
= 3.3V
±
0.3V
Inputs can be driven from 3.3V or 5V components
Available in 48 SSOP, TSSOP packages
Suited to SDRAM applications
DESCRIPTION:
The FCT3932 uses phase-lock loop technology to lock the
frequency and phase of the feedback to the input reference
clock. It provides a large number of low skew outputs that are
configurable in 16 different modes using the CNTRL 1-4
inputs. A dedicated output, Q_FB, is provided to supply the
PLL feedback and it should be connected to the FEEDBACK
input. Q_FB is located adjacent to FEEDBACK to minimize
the delay in the feedback path. In order to offset any delay in
the output path from the FCT3932 output to a receiving device,
100MHz
feedback path delay should be made to match this output path
delay.
The PLL consists of the phase/frequency detector, charge
pump, loop filter and VCO. The FCT3932 requires no external
loop filter components.
The FCT3932 provides 17 outputs grouped in 3 banks with
individual 3-state control and an additional dedicated feed-
back output with no disable. Connecting Q_FB to FEEDBACK
ensures uninterrupted PLL operation when all outputs are
disabled.
Individual bank 3-state allows users to disable unused
outputs in order to limit power dissipation or minimize switch-
ing noise. It also allows users to shut down outputs in low
power modes while maintaining phase lock.
The FCT3932 provides a LOCK pin that goes high when the
device is phase-locked.
The user can bypass the PLL for testability purposes by
deasserting PLL_EN. In this "test" mode, the input frequency
is not limited to the specified range.
The FCT3932 provides an asynchronous reset input,
RST
,
which resets all outputs. This initializes all internal registers so
that outputs start up in a known state.
APPLICATIONS:
SDRAM DIMM Clock, Caches, high speed microproces-
sors, motherboard clock distribution to DIMMs.
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
FUNCTIONAL BLOCK DIAGRAM
3267 drw 01
Phase/Freq.
Detector
FEEDBACK
REF_IN
PLL_EN
Mux
0
1
Charge
Pump &
Loop Filter
Voltage
Controlled
Oscillator
OE
1
Q4
1-4
(BANK 1)
Q8
1-8
(BANK 2)
Q5
1-5
(BANK 3)
Q_FB
C
O
N
T
R
O
L
LOCK
OE
3
CNTRL1-4
OE
2
RST
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT74FCT3932-100PV | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER |
| IDT74FCT32932-100PA | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER |
| IDT74FCT32932-100PV | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER |
| IDT74FCT3932-100 | 3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER |
| IDT74FCT38074 | 3.3V CMOS 1-TO-4 CLOCK DRIVER |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT74FCT399P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT521AP | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT521ASO | 制造商:Integrated Device Technology Inc 功能描述:IDENTITY COMPARATOR, 20 Pin, Plastic, SOP |
| IDT74FCT521ATPYG | 功能描述:IC COMPARATOR IDENTITY 8B 20SSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 比較器 系列:74FCT 標準包裝:1 系列:4000B 類型:幅值比較器 位數(shù):4 輸出:高有效 輸出功能:A<B，A=B，A>B 電源電壓:3 V ~ 18 V 輸出電流高，低:4.2mA，4.2mA 額定電壓和最大 CL 時的最大傳播延遲:350ns @ 15V，50pF 電流 - 靜態(tài):100µA 工作溫度:-55°C ~ 125°C 封裝/外殼:16-SOIC（0.209"，5.30mm 寬） 安裝類型:表面貼裝 包裝:剪切帶 (CT) 其它名稱:296-14121-1 |
| IDT74FCT521ATPYG8 | 功能描述:IC COMPARATOR IDENTITY 8B 20SSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 比較器 系列:74FCT 標準包裝:1 系列:4000B 類型:幅值比較器 位數(shù):4 輸出:高有效 輸出功能:A<B，A=B，A>B 電源電壓:3 V ~ 18 V 輸出電流高，低:4.2mA，4.2mA 額定電壓和最大 CL 時的最大傳播延遲:350ns @ 15V，50pF 電流 - 靜態(tài):100µA 工作溫度:-55°C ~ 125°C 封裝/外殼:16-SOIC（0.209"，5.30mm 寬） 安裝類型:表面貼裝 包裝:剪切帶 (CT) 其它名稱:296-14121-1 |
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