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參數(shù)資料
| 型號： | IDT74FCT388915TEJG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
| 封裝： | GREEN, PLASTIC, LCC-28 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 1140K |
| 代理商： | IDT74FCT388915TEJG |
COMMERCIALTEMPERATURERANGE
IDT74FCT388915T
3.3V LOW SKEW PLL-BASED CMOS CLOCK DRIVER (3-STATE)
1
OCTOBER
2008
COMMERCIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-4243/7
FEATURES:
0.5 MICRON CMOS Technology
Input frequency range: 10MHz – f2Q Max. spec
(FREQ_SEL = HIGH)
Max. output frequency: 150MHz
Pin and function compatible with FCT88915T, MC88915T
5 non-inverting outputs, one inverting output, one 2x output,
one ÷2 output; all outputs are TTL-compatible
3-State outputs
Duty cycle distortion < 500ps (max.)
32/–16mA drive at CMOS output voltage levels
VCC = 3.3V ± 0.3V
Inputs can be driven by 3.3V or 5V components
Available in 28 pin PLCC and SSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74FCT388915T
70/100/133/150
3.3V LOW SKEW PLL-BASED
CMOS CLOCK DRIVER
(WITH 3-STATE)
DESCRIPTION:
The FCT388915T uses phase-lock loop technology to lock the fre-
quency and phase of outputs to the input reference clock. It provides low
skew clock distribution for high performance PCs and workstations. One of
the outputs is fed back to the PLL at the FEEDBACK input resulting in
essentially zero delay across the device. The PLL consists of the phase/
frequency detector, charge pump, loop filter and VCO. The VCO is
designed for a 2Q operating frequency range of 40MHz to f2Q Max.
The FCT388915T provides 8 outputs, the
Q5 output is inverted from the
Q outputs. The 2Q runs at twice the Q frequency and Q/2 runs at half the
Q frequency.
The FREQ_SEL control provides an additional ÷ 2 option in the output
path. PLL _EN allows bypassing of the PLL, which is useful in static test
modes. When PLL_EN is low, SYNC input may be used as a test clock. In
this test mode, the input frequency is not limited to the specified range and
the polarity of outputs is complementary to that in normal operation (PLL_EN
= 1). The LOCK output attains logic HIGH when the PLL is in steady-state
phase and frequency lock. When OE/
RST is low, all the outputs are put in
high impedance state and registers at Q,
Q and Q/2 outputs are reset.
The FCT388915T requires one external loop filter component as
recommended in Figure 3.
Phase/Freq.
Detector
M
u
x
0
1
SYNC (0)
FEED BAC K
SYNC (1)
REF_SEL
PLL_EN
Mux
01
Divide
-By-2
(
÷1)
(
÷2)
1
0
M
u
x
Charge Pum p
Voltage
Controlled
Oscilator
OE/RST
FREQ_SEL
2Q
Q0
Q1
Q2
Q3
Q4
Q5
Q/2
R
D
Q
CP
Q
LF
LOCK
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
R
D
Q
CP
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| IDT74FCT388915T100J8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
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| IDT74FCT388915T133J8 | FCT SERIES, PLL BASED CLOCK DRIVER, 7 TRUE OUTPUT(S), 1 INVERTED OUTPUT(S), PQCC28 |
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| IDT74FCT388915TEJG8 | 功能描述:IC PLL CLK GENERATOR 3ST 28-PLCC RoHS:是 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:74FCT 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
| IDT74FCT399P | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT521AP | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT74FCT521ASO | 制造商:Integrated Device Technology Inc 功能描述:IDENTITY COMPARATOR, 20 Pin, Plastic, SOP |
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