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參數(shù)資料
| 型號(hào)： | IDT74FCT16652TPV8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 202K |
| 代理商： | IDT74FCT16652TPV8 |
1
IDT74FCT16652T/AT/CT
FASTCMOS16-BITBUSTRANSCEIVER/REGISTER
INDUSTRIALTEMPERATURERANGE
JANUARY 2002
IDT74FCT16652T/AT/CT
INDUSTRIAL TEMPERATURE RANGE
FAST CMOS 16-BIT BUS
TRANSCEIVER/REGISTER
DESCRIPTION:
The FCT16652T 16-bit registered transceivers are built using advanced
dual metal CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit bus transceivers with 3-state D-type
registers. For example, the xOEAB and x
OEBAsignalscontrolthetransceiver
functions.
The xSAB and xSBA control pins are provided to select either real time or
storeddatatransfer. Thecircuitryusedforselectcontrolwilleliminatethetypical
decodingglitchthatoccursinamultiplexerduringthetransitionbetweenstored
andrealtimedata.Alowinputlevelselectsreal-timedataandahighlevelselects
stored data.
Data on the A or B data bus, or both, can be stored in the internal D-flip-flops
by low-to-high transitions at the appropriate clock pins (xCLKAB or xCLKBA),
regardless of the select or enable control pins. Flow-through organization of
signalpinssimplifieslayout.Allinputsaredesignedwithhysteresisforimproved
noise margin.
The FCT16652T is ideally suited for driving high capacitance loads and low-
impedancebackplanes.Theoutputbuffersaredesignedwithpoweroffdisable
capability to allow "live insertion" of boards when used as backplane drivers.
1
A1
1
OE BA
1
CLKBA
1
SBA
1
CLKAB
1
SAB
1
OE AB
1
B1
B REG
A R EG
D
C
D
TO SEV E N O THER C HAN NELS
2
B 1
2
CLK AB
2
OE BA
2
CLK BA
2
SBA
2
A1
2
OE AB
2
SAB
TO SEV E N O THER C HAN NELS
B R EG
A R EG
D
C
D
FEATURES:
0.5 MICRON CMOS Technology
High-speed, low-power CMOS replacement for ABT functions
Typical tSK(o) (Output Skew) < 250ps
Low input and output leakage
≤≤≤≤≤1A (max.)
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 5V ±10%
High drive outputs (–32mA IOH, 64mA IOL)
Power off disable outputs permit “l(fā)ive insertion”
Typical VOLP (Output Ground Bounce) < 1.0V at VCC = 5V,
TA = 25°C
Available in SSOP and TSSOP packages
FUNCTIONAL BLOCK DIAGRAM
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2002 Integrated Device Technology, Inc.
DSC-5450/1
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