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參數(shù)資料
| 型號(hào)： | IDT74FCT162543TPV |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | FAST CMOS 16-BIT LATCHED TRANSCEIVER |
| 中文描述： | FCT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | SSOP-56 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 127K |
| 代理商： | IDT74FCT162543TPV |
Integrated Device Technology, Inc.
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SEPTEMBER 1996
1996 Integrated Device Technology, Inc.
5.12
DSC-2618/7
1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST CMOS
16-BIT LATCHED
TRANSCEIVER
FEATURES:
Common features:
–
0.5 MICRON CMOS Technology
–
High-speed, low-power CMOS replacement for
ABT functions
–
Typical t
SK
(o) (Output Skew) < 250ps
–
Low input and output leakage
≤
1
μ
A (max.)
–
ESD > 2000V per MIL-STD-883, Method 3015;
> 200V using machine model (C = 200pF, R = 0)
–
Packages include 25 mil pitch SSOP, 19.6 mil pitch
TSSOP, 15.7 mil pitch TVSOP and 25 mil pitch Cerpack
–
Extended commercial range of -40
°
C to +85
°
C
–
V
CC
= 5V
±
10%
Features for FCT16543T/AT/CT/ET:
–
High drive outputs (-32mA I
OH
, 64mA I
OL
)
–
Power off disable outputs permit “l(fā)ive insertion”
–
Typical V
OLP
(Output Ground Bounce) < 1.0V at
V
CC
= 5V, T
A
= 25
°
C
Features for FCT162543T/AT/CT/ET:
–
Balanced Output Drivers:
±
24mA (commercial),
±
16mA (military)
–
–
Reduced system switching noise
Typical V
OLP
(Output Ground Bounce) < 0.6V at
V
CC
= 5V,T
A
= 25
°
C
IDT54/74FCT16543T/AT/CT/ET
IDT54/74FCT162543T/AT/CT/ET
FUNCTIONAL BLOCK DIAGRAM
1
OEBA
D
C
D
C
1
B
1
1
CEBA
1
LEBA
1
OEAB
1
CEAB
1
A
1
1
LEAB
TO 7 OTHER CHANNELS
2618 drw 01
2
OEBA
2
CEBA
2
LEBA
D
C
2
OEAB
2
CEAB
2
A
1
2
B
1
2
LEAB
TO 7 OTHER CHANNELS
2618 drw 02
D
C
DESCRIPTION:
The FCT16543T/AT/CT/ET and FCT162543T/AT/CT/ET
16-bit latched transceivers are built using advanced dual metal
CMOS technology. These high-speed, low-power devices are
organized as two independent 8-bit D-type latched transceiv-
ers with separate input and output control to permit indepen-
dent control of data flow in either direction. For example, the A-
to-B Enable (x
CEAB
) must be LOW in order to enter data from
the A port or to output data from the B port. x
LEAB
controls the
latch function. When x
LEAB
is LOW, the latches are transpar-
ent. A subsequent LOW-to-HIGH transition of x
LEAB
signal
puts the A latches in the storage mode. x
OEAB
performs output
enable function on the B port. Data flow from the B port to the
A port is similar but requires using x
CEBA
, x
LEBA
, and x
OEBA
inputs. Flow-through organization of signal pins simplifies
layout. All inputs are designed with hysteresis for improved
noise margin.
The FCT16543T/AT/CT/ET are ideally suited for driving
high-capacitance loads and low-impedance backplanes. The
output buffers are designed with power off disable capability to
allow "live insertion" of boards when used as backplane drivers.
The FCT162543T/AT/CT/ET have balanced output drive
with current limiting resistors. This offers low ground bounce,
minimal undershoot, and controlled output fall times–reducing
the need for external series terminating resistors. The
FCT162543T/AT/CT/ET are plug-in replacements for the
FCT16543T/AT/CT/ET and 54/74ABT16543 for on-board bus
interface applications.
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參數(shù)描述 |
|---|---|
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| IDT74FCT162823ATPAG | 功能描述:IC REGISTER 18BIT FAST 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:74FCT 標(biāo)準(zhǔn)包裝:1 系列:74LVX 功能:主復(fù)位 類型:D 型總線 輸出類型:非反相 元件數(shù):1 每個(gè)元件的位元數(shù):8 頻率 - 時(shí)鐘:150MHz 延遲時(shí)間 - 傳輸:7.1ns 觸發(fā)器類型:正邊沿 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 包裝:Digi-Reel® 其它名稱:74LVX273MTCXDKR |
| IDT74FCT162823ATPAG8 | 功能描述:IC REGISTER 18BIT FAST 56-TSSOP RoHS:是 類別:集成電路 (IC) >> 邏輯 - 觸發(fā)器 系列:74FCT 標(biāo)準(zhǔn)包裝:1 系列:74LVX 功能:主復(fù)位 類型:D 型總線 輸出類型:非反相 元件數(shù):1 每個(gè)元件的位元數(shù):8 頻率 - 時(shí)鐘:150MHz 延遲時(shí)間 - 傳輸:7.1ns 觸發(fā)器類型:正邊沿 輸出電流高，低:4mA，4mA 電源電壓:2 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:20-TSSOP（0.173"，4.40mm 寬） 包裝:Digi-Reel® 其它名稱:74LVX273MTCXDKR |
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