參數(shù)資料
型號(hào): IDT74FCT162511CTPVG
廠商: IDT, Integrated Device Technology Inc
文件頁(yè)數(shù): 9/10頁(yè)
文件大?。?/td> 0K
描述: IC REGISTERD TRCVR 16BIT 56SSOP
標(biāo)準(zhǔn)包裝: 26
系列: 74FCT
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 16
輸出電流高,低: 24mA,24mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 管件
其它名稱: 74FCT162511CTPVG
8
MILITARYANDINDUSTRIALTEMPERATURERANGES
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
FCT162511AT
FCT162511CT
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Test Conditions(1, 3)
Min. Max. Min. Max. Min. Max. Min. Max. Unit
tSU
Set-upTime
GEN/CHK LOW
PBx valid
CL = 50pF
4
4
3
3.5
ns
HIGH or LOW
PBx not valid
RL = 500
Ω
3
3—
ns
Ax to CLKAB
GEN/CHK HIGH
PERB valid
4
4
3
3
ns
PERB not valid
3
3
3
3
ns
tSU
Set-upTime
GEN/CHK HIGH
PERB valid
4
4
3
3
ns
PAx to CLKAB
PERB not valid
3
3
3
3
ns
tSU
Set-upTime
PERA valid
4
4
3
3
ns
Bx to CLKBA,
PERA not valid
3
4
3
3
ns
PBx to CLKBA
tSU
Set-upTime
CLKAB LOW
PBx valid
3.5
3.5
3
3
ns
Ax to LEAB
GEN/CHK LOW
PBx not valid
3
3
3
3
ns
CLKAB LOW
PERB valid
3.5
3.5
3
3
ns
GEN/CHK HIGH
PERB not valid
3
3
3
3
ns
CLKAB HIGH
PBx valid
3.5
3.5
3
3
ns
GEN/CHK LOW
PBx not valid
3
3
3
3
ns
CLKAB HIGH
PERB valid
3.5
3.5
3
3
ns
GEN/CHK HIGH
PERB not valid
3
3
3
3
ns
tSU
Set-upTime
CLKAB LOW
PERB valid
3.5
3.5
3
3
ns
PAx to LEAB
GEN/CHK HIGH
PERB not valid
3
3
3
3
ns
CLKAB HIGH
PERB valid
3.5
3.5
3
3
ns
GEN/CHK HIGH
PERB not valid
3
3
3
3
ns
tSU
Set-upTime
CLKBA LOW
PERA valid
3.5
3.5
3
3
ns
Bx to LEBA
PERA not valid
3
3
3
3
ns
PBx to LEBA
CLKBA HIGH
PERA valid
3.5
3.5
3
3
ns
PERA not valid
3
3
3
3
ns
tSK(O)
Output Skew(4)
0.5
0.5
0.5
0.5
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (SET UP TIMES)
FCT162511AT
FCT162511CT
Ind.
Mil.
Ind.
Mil.
Symbol
Parameter
Condition(1)
Min. Max. Min. Max. Min. Max.
Min. Max. Unit
tH
Hold Time HIGH or LOW Ax to LEAB, Bx to LEBA
CL= 50pF
1
1
1
1
ns
tH
Hold Time HIGH or LOW PAx to LEAB
RL = 500
Ω
1—
1
ns
tH
Hold Time HIGH or LOW PBx to LEBA
1
1
1
1
ns
tH
Hold Time Ax to CLKAB, PAx to CLKAB
1
1
0
0
ns
tH
Hold Time Bx to CLKBA, PBx to CLKBA
1
1
0
0
ns
tW
LEAB or LEBA Pulse Width HIGH(2)
3—
3
ns
tW
CLKAB or CLKBA Pulse Width HIGH or LOW(2)
3—
3
ns
SWITCHING CHARACTERISTICS OVER OPERATING RANGE (HOLD TIMES)
NOTES:
1. See test circuits and waveforms.
2. This parameter is guaranteed but not tested.
3. "Not valid" means the set-up time indicated is not sufficient to assure proper functioning of this output; however, the set-up time indicated will assure proper functioning of the
A to B or B to A port respective to the indicated direction.
4. Skew between any two outputs of the same package, switching in the same direction, excluding
PERx in clocked mode, and Pxx (parity bits) and PERx in transparent/
latched mode. This parameter is guaranteed by design.
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