參數(shù)資料
型號(hào): IDT74FCT162511ATPVG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 5/10頁
文件大?。?/td> 0K
描述: IC REGISTERD TRCVR 16BIT 56SSOP
標(biāo)準(zhǔn)包裝: 26
系列: 74FCT
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 16
輸出電流高,低: 24mA,24mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-BSSOP(0.295",7.50mm 寬)
供應(yīng)商設(shè)備封裝: 56-SSOP
包裝: 管件
其它名稱: 74FCT162511ATPVG
4
MILITARYANDINDUSTRIALTEMPERATURERANGES
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
NOTES:
1. Conditions shown are for
GEN/CHK = H, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A parity checking is similar but uses
OEBA = L, OEAB
= H and errors will be indicated on
PERA.
3. In parity checking mode the parity bits will be transmitted unchanged along with the
corresponding data regardless of parity errors (PB1 = PA1).
4. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge triggered
clock.
5. Conditions shown are for the byte A0–A7 and PA1. The byte A8–A15 and PA2 is similiar.
6. The parity error flag
PERB is a combined flag for both bytes A0–A7 and A8–A15. If a parity
error occurs on either byte
PERB will go low. PERB is an open drain output which must
be externally pulled up to achieve a logic HIGH.
NOTES:
1. Conditions shown are for
GEN/CHK = L, OEAB = L, OEBA = H.
2. A-to-B parity checking is shown. B-to-A is capable of parity checking while A-to-B
is performing generation. B-to-A will not generate parity.
3. The response shown is for LEAB = H. If LEAB = L then CLKAB will control as an edge
triggered clock.
4. Conditions shown are for the byte A–A7. The byte A8–A15 is similiar but will output
the parity on PB2.
5. The error flag
PERB will remain in a high state during parity generation.
FUNCTION TABLE(1, 4)
NOTES:
1. A-to-B data flow is shown. B-to-A data flow is similar but uses
OEBA, LEBA,
and CLKBA.
2. Output level before the indicated steady-state input conditions were established.
3. Output level before the indicated steady-state input conditions were established,
provided that CLKAB was HIGH before LEAB went LOW.
4. H = HIGH Voltage Level
L = LOW Voltage Level
X = Don't Care
Z = High-impedance
↑ = LOW-to-HIGH Transition
Inputs
Outputs
OEAB
LEAB
CLKAB
Ax
Bx
HX
X
Z
LH
X
L
LH
X
H
LL
LL
HH
LL
L
X
B(2)
LL
H
X
B(3)
A0 – A7
Number of inputs that are high
ODD/
EVEN
PB1
1, 3, 5 or 7
L
H
1, 3, 5 or 7
H
L
0, 2, 4, 6 or 8
L
0, 2, 4, 6 or 8
H
A0 – A7 and PA1(5)
Number of inputs that are high
ODD/
EVEN
PERB
1, 3, 5, 7 or 9
L
1, 3, 5, 7 or 9
H
H(6)
0, 2, 4, 6 or 8
L
H(6)
0, 2, 4, 6 or 8
H
L
FUNCTION TABLE
(PARITY CHECKING) (1, 2, 3, 4)
FUNCTION TABLE
(PARITY GENERATION) (1, 2, 3, 4, 5)
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