參數(shù)資料
型號(hào): IDT74FCT162511ATPAG8
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 4/10頁
文件大?。?/td> 0K
描述: IC REGISTERD TRCVR 16BIT 56TSSOP
標(biāo)準(zhǔn)包裝: 2,000
系列: 74FCT
邏輯類型: 寄存收發(fā)器,非反相
元件數(shù): 1
每個(gè)元件的位元數(shù): 16
輸出電流高,低: 24mA,24mA
電源電壓: 4.5 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.240",6.10mm 寬)
供應(yīng)商設(shè)備封裝: 56-TSSOP
包裝: 帶卷 (TR)
其它名稱: 74FCT162511ATPAG8
3
IDT54/74FCT162511AT/CT
FASTCMOS16-BITREGISTERED/LATCHEDTRANSCEIVER
MILITARYANDINDUSTRIALTEMPERATURERANGES
SSOP/ TSSOP/ CERPACK
TOP VIEW
PIN CONFIGURATION
GEN/CHK
B0
B1
GND
B2
B3
VCC
B4
B6
PB1
B7
PERB
GND
B8
B5
B9
B11
VCC
B12
B10
CLKAB
B14
B13
B15
GND
PB2
CLKBA
ODD/EVEN
OEAB
LEAB
PA1
GND
A0
A1
VCC
A2
A3
A5
A4
A6
A7
GND
A10
PERA
A8
VCC
A9
PA2
A12
A11
A14
GND
A15
LEBA
A13
OEBA
47
37
38
39
40
41
42
43
44
45
46
33
34
35
36
56
55
49
50
51
52
53
54
48
1
2
3
4
5
6
7
8
9
10
12
13
14
15
16
17
18
19
20
11
21
22
23
24
29
30
31
32
25
26
27
28
Symbol
Description
Max
Unit
VTERM(2)
Terminal Voltage with Respect to GND
–0.5 to 7
V
VTERM(3)
Terminal Voltage with Respect to GND
–0.5 to VCC+0.5
V
TSTG
Storage Temperature
–65 to +150
° C
IOUT
DC Output Current
–60 to +120
mA
ABSOLUTE MAXIMUM RATINGS(1)
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. All device terminals except FCT162XXX Output and I/O terminals.
3. Output and I/O terminals for FCT162XXX.
Symbol
Parameter(1)
Conditions
Typ.
Max.
Unit
CIN
Input Capacitance
VIN = 0V
3.5
6
pF
CI/O
I/O Capacitance
VOUT = 0V
3.5
8
pF
CO
Open Drain
VOUT = 0V
3.5
6
pF
Capacitance
CAPACITANCE (TA = +25°C, F = 1.0MHz)
PIN DESCRIPTION
Pin Names
Description
OEAB
A-to-B Output Enable Input (Active LOW)
OEBA
B-to-A Output Enable Input (Active LOW)
LEAB
A-to-B Latch Enable Input
LEBA
B-to-A Latch Enable Input
CLKAB
A-to-B Clock Input
CLKBA
B-to-A Clock Input
A x
A-to-B Data Inputs or B-to-A 3-State Outputs
B x
B-to-A Data Inputs or A-to-B 3-State Outputs
PERA
Parity Error (Open Drain) on A Outputs
PERB
Parity Error (Open Drain) on B Outputs
PAx(1)
A-to-B Parity Input, B-to-A Parity Output
PBx
B-to-A Parity Input, A-to-B Parity Output
ODD/
EVEN
Parity Mode Selection Input
GEN/CHK
A to B Port Generate or Check Mode Input
NOTE:
1. The PAx pin input is internally disabled during parity generation. This means that when
generating parity in the A to B direction there is no need to add a pull up resistor to
guarantee state. The pin will still function properly as the parity output for the B to A
direction.
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