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參數資料
| 型號： | IDT74CBTLVR3384PGG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | CBTLV/3B SERIES, 10-BIT DRIVER, TRUE OUTPUT, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數： | 4/5頁 |
| 文件大?。?/td> | 65K |
| 代理商： | IDT74CBTLVR3384PGG |
4
INDUSTRIALTEMPERATURERANGE
IDT74CBTLVR3384
LOW-VOLTAGE 10-BIT BUS SWITCH
Open
VLOAD
GND
VCC
Pulse
Generator
D.U.T.
500
Ω
500
Ω
CL
RT
VIN
VOUT
(1, 2)
SAME PHASE
INPUT TRANSITION
OPPOSITE PHASE
INPUT TRANSITION
0V
VOH
VOL
tPLH
tPHL
tPLH
OUTPUT
VIH
VT
VIH
VT
CONTROL
INPUT
tPLZ
0V
OUTPUT
NORMALLY
LOW
tPZH
0V
SWITCH
CLOSED
OUTPUT
NORMALLY
HIGH
ENABLE
DISABLE
SWITCH
OPEN
tPHZ
0V
VOL + VLZ
VOH
VT
tPZL
VLOAD/2
VIH
VT
VOL
VOH -VHZ
TEST CIRCUITS AND WAVEFORMS
Propagation Delay
Test Circuits for All Outputs
Enable and Disable Times
NOTE:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH.
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
NOTES:
1. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2.5ns; tR ≤ 2.5ns.
2. Pulse Generator for All Pulses: Rate
≤ 10MHz; tF ≤ 2ns; tR ≤ 2ns.
Test
Switch
tPLZ/tPZL
VLOAD
tPHZ/tPZH
GND
tPD
Open
SWITCH POSITION
Symbol
VCC
(1)= 3.3V±0.3V
VCC
(2)= 2.5V±0.2V
Unit
VLOAD
6
2 x Vcc
V
VIH
3
Vcc
V
VT
1.5
Vcc / 2
V
VLZ
300
150
mV
VHZ
300
150
mV
CL
50
30
pF
TEST CONDITIONS
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