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參數(shù)資料
| 型號(hào)： | IDT74ALVCH16841PA8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 總線收發(fā)器 |
| 英文描述： | ALVC/VCX/A SERIES, DUAL 10-BIT DRIVER, TRUE OUTPUT, PDSO56 |
| 封裝： | 0.50 MM PITCH, TSSOP-56 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 66K |
| 代理商： | IDT74ALVCH16841PA8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16841
3.3VCMOS20-BITBUS-INTERACED-TYPELATCHWITH3-STATEOUTPUTS
1
MARCH 1999
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
DSC-4699/2
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in SSOP, TSSOP, and TVSOP packages
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCH16841
3.3V CMOS 20-BIT
BUS-INTERFACE D-TYPE
LATCH WITH 3-STATE OUT-
PUTS AND BUS-HOLD
DESCRIPTION:
This20-bitinterfaceD-typelatchisbuiltusingadvanceddualmetalCMOS
technology. The ALVCH16841 features 3-state outputs designed specifi-
cally for driving highly capacitive relatively low-impedance loads. This
device is particularly suitable for implementing buffer registers, unidirec-
tional bus drivers, and working registers.
The ALVCH16841 can be used as two 10-bit latches or one 20-bit latch.
The 20 latches are transparent D-type latches. The device has noninverting
data (D) inputs and provides true data at its outputs. While the latch-enable
(1LE or 2LE) input is high, the Q outputs of the corresponding 10-bit latch
follow the D inputs. When LE is taken low, the Q outputs are latched at the
levels set up at the D inputs.
A buffered output-enable (1OE or 2OE) input can be used to place the
outputs of the corresponding 10-bit latch in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state,
the outputs neither load nor drive the bus lines significantly. OE does not
affect the internal operation of the latches. Old data can be retained or new
data can be entered while the outputs are in the high-impedance state.
The ALVCH16841 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
The ALVCH16841 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating
inputs and eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
1
D
C 1
TO NINE OTHER CHANNELS
1
LE
1
OE
1
D 1
1
Q1
1
D
C1
TO NINE OTH ER C HAN NELS
2
LE
2
OE
2
D 1
2
Q 1
1
56
55
2
28
29
42
15
Q
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