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參數(shù)資料
| 型號： | IDT74ALVCH16652 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | 3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER WITH 3-STATE OUTPUTS AND BUS-HOLD |
| 中文描述： | 3.3V的CMOS 16位總線收發(fā)器和登記注冊三態(tài)輸出和總線狀態(tài)保持 |
| 文件頁數(shù)： | 1/8頁 |
| 文件大?。?/td> | 119K |
| 代理商： | IDT74ALVCH16652 |
INDUSTRIAL TEMPERATURE RANGE
IDT74ALVCH16652
3.3V CMOS 16-BIT BUS TRANSCEIVER AND REGISTER
1
J ANUARY 2004
INDUS T RIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2004 Integrated Device Technology, Inc.
DSC-4526/2
FEATURES:
0.5 MICRON CMOS Technology
Typical t
SK(o)
(Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
V
CC
= 3.3V ± 0.3V, Normal Range
V
CC
= 2.7V to 3.6V, Extended Range
V
CC
= 2.5V ± 0.2V
CMOS power levels (0.4
μ
W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
DE S CRIPT ION:
This 16-bit bus transceiver and register is built using advanced dual metal
CMOS technology. The ALVCH16652 consists of D-type flip-flops and control
circuitry arranged for multiplexed transmssion of data directly fromthe data bus
or fromthe internal storage registers. The device can be used as two 8-bit
transceivers or one 16-bit transceiver.
Complementary output enable (OEAB and
OEBA
) inputs are provided to
control the transceiver functions. Select control (SAB and SBA) inputs are
provided to select whether real-time or stored data is transferred. A low input
level selects real-time data, and a high input level selects stored data. Circuitry
used for select control elimnates the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time data. Data on the
A or B bus, or both, can be stored in the internal D flip-flops by low-to-high
transition at the appropriate clock (CLKAB or CLKBA) inputs regardless of the
levels on the select control or output enable inputs. When SAB and SBA are in
the real-time transfer mode, it also is possible to store data without using the
internal D-type flip-flops by simultaneously enabling OEAB and
OEBA
. In this
configuration, each output reinforces its input. Thus, when all other data sources
to the two sets of bus lines are in the high-impedance state, each set of bus lines
remains at its last level configuration.
The ALVCH16652 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16652 has “bus-hold” which retains the inputs’ last state
whenever the input bus goes to a high impedance. This prevents floating inputs
and elimnates the need for pull-up/down resistors.
DRIV E FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
IDT74ALVCH16652
3.3V CMOS 16-BIT BUS
TRANSCEIVER AND
REGISTER WITH 3-STATE
OUTPUTS AND BUS-HOLD
TO 7 OTHER CHANNELS
1
B
1
D
C
D
C
1
A
1
1
SAB
1
CLKAB
1
SBA
1
OEBA
1
CLKBA
56
55
54
2
3
5
52
1
OEAB
1
A REG
B REG
TO 7 OTHER CHANNELS
2
B
1
D
C
D
C
2
A
1
2
SAB
2
CLKAB
2
SBA
2
OEBA
2
CLKBA
29
30
31
27
26
15
42
2
OEAB
28
A REG
B REG
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