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參數(shù)資料
| 型號(hào)： | IDT74ALVCH16260PAG8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 編、解碼器及復(fù)用、解復(fù)用 |
| 英文描述： | ALVC/VCX/A SERIES, 12 1 LINE TO 2 LINE MULTIPLEXER AND DEMUX/DECODER, TRUE OUTPUT, PDSO56 |
| 封裝： | GREEN, TSSOP-56 |
| 文件頁數(shù)： | 1/7頁 |
| 文件大?。?/td> | 82K |
| 代理商： | IDT74ALVCH16260PAG8 |
INDUSTRIALTEMPERATURERANGE
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH
1
MARCH 2006
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2006 Integrated Device Technology, Inc.
DSC-4737/5
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TSSOP package
FUNCTIONAL BLOCK DIAGRAM
IDT74ALVCH16260
3.3V CMOS 12-BIT TO 24-BIT
MULTIPLEXED D-TYPE LATCH
WITH 3-STATE OUTPUTS
AND BUS-HOLD
DESCRIPTION:
This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual
metal CMOS technology. The ALVCH16260 is used in applications in which
two separate data paths must be multiplexed onto, or demultiplexed from, a
singledatapath.Typicalapplicationsincludemultiplexingand/ordemultiplexing
addressanddatainformationinmicroprocessororbus-interfaceapplications.
This device also is useful in memory interleaving applications.
Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available
foraddressand/ordatatransfer.Theoutput-enable(
OE1B,OE2B,andOEA)
inputs control the bus transceiver functions. The
OE1B and OE2B control
signals also allow bank control in the A-to-B direction. Address and/or data
informationcanbestoredusingtheinternalstoragelatches.Thelatch-enable
(LE1B, LE2B, LEA1B, and LEA2B) inputs are used to control data storage.
When the latch-enable input is high, the latch is transparent. When the latch-
enable input goes low, the data present at the inputs is latched and remains
latched until the latch-enable input is returned high.
The ALVCH16260 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining speed
performance.
The ALVCH16260 has “bus-hold” which retains the inputs’ last state
whenever the input goes to a high impedance. This prevents floating inputs
and eliminates the need for pull-up/down resistors.
APPLICATIONS:
3.3V high speed systems
3.3V and lower voltage computing systems
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
LE1B
LEA1B
OE1B
SEL
OEA
A1:12
LE2B
LEA2B
OE2B
A-1B
LATCH
1B-A
LATCH
A-2B
LATCH
2B-A
LATCH
M
U
X
1
0
12
1
B1:12
2
B1:12
12
30
29
2
28
1
27
55
56
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