參數(shù)資料
型號: IDT74ALVC16835PFG
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 1/6頁
文件大小: 0K
描述: IC UNIV BUS DVR 18BIT 56TVSOP
產(chǎn)品變化通告: Product Discontinuaton 29/Apr/2011
標(biāo)準(zhǔn)包裝: 43
系列: 74ALVC
邏輯類型: 通用總線驅(qū)動器,CMOS
電路數(shù): 18 位
輸出電流高,低: 24mA,24mA
電源電壓: 2.3 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 56-TFSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 56-TVSOP
包裝: 管件
其它名稱: 74ALVC16835PFG
INDUSTRIALTEMPERATURERANGE
IDT74ALVC16835
3.3V CMOS 18-BIT UNIVERSAL BUS DRIVER WITH 3-STATE OUTPUTS
1
JUNE 2009
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
2009 Integrated Device Technology, Inc.
DSC-4478/6
FEATURES:
0.5 MICRON CMOS Technology
Typical tSK(o) (Output Skew) < 250ps
ESD > 2000V per MIL-STD-883, Method 3015; > 200V using
machine model (C = 200pF, R = 0)
VCC = 3.3V ± 0.3V, Normal Range
VCC = 2.7V to 3.6V, Extended Range
VCC = 2.5V ± 0.2V
CMOS power levels (0.4
μμμμμ W typ. static)
Rail-to-Rail output swing for increased noise margin
Available in TVSOP package
FUNCTIONAL BLOCK DIAGRAM
DRIVE FEATURES:
High Output Drivers: ±24mA
Suitable for heavy loads
IDT74ALVC16835
3.3V CMOS 18-BIT
UNIVERSAL BUS DRIVER
WITH 3-STATE OUTPUTS
DESCRIPTION:
This 18-bit universal bus driver is built using advanced dual metal
CMOS technology. Data flow from A to Y is controlled by the output-enable
(
OE) input. The device operates in the transparent mode when the latch-
enable (LE) input is high. The A data is latched if the clock (CLK) input is
held at a high or low logic level. If LE is low, the A data is stored in the latch
flip-flop on the low-to-high transition of CLK. When
OE is high, the outputs
are in the high-impedance state.
The ALVC16835 has been designed with a ±24mA output driver. This
driver is capable of driving a moderate to heavy load while maintaining
speed performance.
LE
A1
TO 17 OTHER CHANNELS
OE
CLK
27
54
28
30
1
D
CLK
3
Y1
C1
APPLICATIONS:
SDRAM Modules
PC Motherboards
Workstations
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