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參數(shù)資料
| 型號： | IDT7383L30GB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 位片處理器 |
| 英文描述： | HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM |
| 中文描述： | 16-BIT, BIT-SLICE MICROPROCESSOR, CPGA68 |
| 封裝： | CAVITY-UP, PGA-68 |
| 文件頁數(shù)： | 5/7頁 |
| 文件大?。?/td> | 72K |
| 代理商： | IDT7383L30GB |
6.11
5
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7014S12
Com'l. Only
Min.
7014S15
Com'l. Only
Min.
7014S20
7014S25
7014S35
Mil. Only
Min.
Symbol
WRITE CYCLE
t
WC
t
AW
t
AS
t
WP
t
WR
t
DW
Parameter
Max.
Max.
Min.
Max.
Min.
Max.
Max.
Unit
Write Cycle Time
Address Valid to End-of-Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data Valid to End-of-Write
Output High-Z Time
(1, 2)
Data Hold Time
(3)
Write Enabled to Output in High-Z
(1, 2)
12
10
0
10
1
8
—
—
—
—
—
—
15
14
0
12
1
10
—
—
—
—
—
—
20
15
0
15
2
12
—
—
—
—
—
—
25
20
0
20
2
15
—
—
—
—
—
—
35
30
0
30
2
25
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
t
HZ
—
7
—
7
—
9
—
11
—
15
ns
t
DH
0
—
0
—
0
—
0
—
0
—
ns
t
WZ
—
7
—
7
—
9
—
11
—
15
ns
t
OW
Output Active from End-of-Write
(1, 2, 3)
Write Pulse to Data Delay
(4)
Write Data Valid to Read Data Delay
(4)
0
—
0
—
0
—
0
—
0
—
ns
t
WDD
—
25
—
30
—
40
—
45
—
55
ns
t
DDD
—
22
—
25
—
30
—
35
—
45
ns
NOTES:
1. Transition is measured
±
200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary
over voltage and temperature, the actual t
DH
will always be smaller than the actual t
OW
.
4. Port-to-port delay through RAM cells from writing port to reading port, refer to “Timing Waveform of Write With Port-to-Port Read”.
2528 tbl 09
2528 drw 09
R/
W
"A"
VALID
t
WC
MATCH
VALID
MATCH
t
WP
t
DW
t
WDD
t
DDD
ADDR
"A"
DATA
IN "A"
DATA
OUT "B"
ADDR
"B"
t
DH
TIMING WAVEFORM OF WRITE WITH PORT-TO-PORT READ
(1,2)
NOTES:
1. R/
W
"B"
= V
IH
, Read cycle pass through.
2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is opposite from port "A".
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
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