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參數(shù)資料
| 型號(hào)： | IDT73720 |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | Octal Buffers And Line/MOS Drivers With 3-State Outputs 20-PDIP -40 to 85 |
| 中文描述： | 16位的三端口總線交換 |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 74K |
| 代理商： | IDT73720 |
IDT73720 /A16-BIT TRI-PORT BUS EXCHANGER
COMMERCIAL TEMPERATURE RANGE
11.5
7
SWITCH POSITION
Test
Switch
Closed
Disable LOW
Enable LOW
All Other Tests
Open
DEFINITIONS:
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to Z
OUT
of the Pulse
Generator.
2527 tbl 08
TEST CIRCUITS AND WAVEFORMS
Figure 5. Test Circuit for all outputs
Pulse
Generator
R
T
D.U.T.
V
CC
V
IN
C
L
V
OUT
50pF
500
500
7.0V
2527 drw 07
AC ELECTRICAL CHARACTERISTICS
(V
CC
= 5.0V
±
5%, T
A
= 0
°
to +70
°
C)
73720A
73720
Symbol
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
PLH
t
PHL
t
HZ
t
LZ
t
ZH
t
ZL
t
HZ
t
LZ
t
ZH
t
ZL
t
SU
t
H
t
W
Parameter
Test Conditions
(1)
C
L
= 50pF
R
L
= 500 Ohms
Min.
(2)
2.0
Max.
6.0
Min.
(2)
2.0
Max.
7.5
Units
ns
X to Y & X to Z Latches enabled
Y to X & Z to X Latches enabled
2.0
6.0
2.0
7.5
ns
Latch Enable to Y & Z Port
LEXY to Y
LEXZ to Z
LEYX to X
LEZX to X
2.0
7.0
2.0
8.5
ns
Latch Enable to X
2.0
7.0
2.0
8.5
ns
Path to X Port Propagation Delay
2.0
7.0
2.0
8.5
ns
Y & Z Port Disable Time (T/
R
, PATH,
OEU
,
OEL
)
(3)
2.0
8.5
2.0
9.5
ns
Y & Z Port Enable Time (T/
R
, PATH,
OEU
,
OEL
)
(3)
2.0
9.5
2.0
10.5
ns
X-Port DisableTime (T/
R
,
OEU
,
OEL
)
(3)
2.0
8.5
2.0
9.5
ns
X-Port Enable Time (T/
R
,
OEU
,
OEL
)
(3)
2.0
9.5
2.0
10.5
ns
Port to LE Set-up time
Port to LE Hold time
LE Pulse Width, HIGH or LOW
(2)
2.0
1.5
3
—
—
—
2.0
1.5
4
—
—
—
ns
ns
ns
NOTES:
1. All timings are referenced to 1.5 V.
2. Minimum Delay Times, Enable Times, Disable Times and Pulse Width are guaranteed by design, but not tested.
3. Bus turnaround times are guaranteed by design, but not tested. (T/
R
enable/disable times).
2527 tbl 07
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