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參數(shù)資料
| 型號： | IDT72V85L20PA |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 7/12頁 |
| 文件大小： | 0K |
| 描述： | IC FIFO ASYNC DUAL 20NS 56-TSSOP |
| 標準包裝： | 34 |
| 系列： | 72V |
| 功能： | 異步 |
| 存儲容量： | 72K（4K x 18） |
| 訪問時間： | 20ns |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 56-TFSOP（0.240"，6.10mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 56-TSSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1255 (CN2011-ZH PDF) |
| 其它名稱： | 72V85L20PA 800-1540 800-1540-5 800-1540-ND |
4
COMMERCIAL ANDINDUSTRIAL
TEMPERATURERANGES
IDT72V81/72V82/72V83/72V84/72V85 3.3V CMOS DUAL ASYNCHRONOUS FIFO
512 x 9, 1024 x 9, 2048 x 9, 4096 x 9, 8192 x 9
Single Device Mode, this pin acts as the retransmit input. The Single Device
Mode is initiated by grounding the Expansion In (XI).
The IDT72V81/72V82/72V83/72V84/72V85 can be made to retransmit
datawhentheRetransmitEnablecontrol(RT)inputispulsedlow. Aretransmit
operationwillsettheinternalreadpointertothefirstlocationandwillnotaffect
the write pointer. Read Enable (R) and Write Enable (W) must be in the high
stateduringretransmitfortheIDT72V81/72V82/72V83/72V84/72V85respec-
tively.Thisfeatureisusefulwhenlessthan512/1,024/2,048/4,096/8,192writes
areperformedbetweenresets.Theretransmitfeatureisnotcompatiblewiththe
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN ( XI )
Thisinputisadual-purposepin. ExpansionIn(XI)isgroundedtoindicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG ( FF )
TheFullFlag(FF)willgolow,inhibitingfurtherwriteoperation,whenthewrite
pointerisonelocationlessthanthereadpointer,indicatingthatthedeviceisfull.
If the read pointer is not moved after Reset (RS), the Full-Flag (FF) will go low
after 512 writes for the IDT72V81, 1,024 writes for the IDT72V82, 2,048 writes
for the IDT72V83, 4,096 writes for the IDT72V84 and 8,192 writes for the
IDT72V85.
EMPTY FLAG ( EF )
The Empty Flag (EF) will go low, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG ( XO/HF )
This is a dual-purpose output. In the single device mode, when Expan-
sionIn(XI)isgrounded,thisoutputactsasanindicationofahalf-fullmemory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set low and will remain set until the
difference between the write pointer and read pointer is less than or equal
toonehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by using rising edge of the read operation.
IntheDepthExpansionMode,ExpansionIn(XI)isconnectedtoExpansion
Out (XO) of the previous device in the Daisy Chain by providing a pulse to the
next device when the previous device reaches the last location of memory.
DATA OUTPUTS ( Q0 – Q8 )
Data outputs for 9-bit wide data. This data is in a high impedance
condition whenever Read (R) is in a high state.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET ( RS )
ResetisaccomplishedwhenevertheReset(RS)inputistakentoalowstate.
During reset, both internal read and write pointers are set to the first location.
Aresetisrequiredafterpowerupbeforeawriteoperationcantakeplace.Both
the Read Enable ( R) and Write Enable ( W) inputs must be in the high
state during the window shown in Figure 2, (i.e., tRSS before the rising
edge of RS ) and should not change until tRSR after the rising edge of
RS. Half-Full Flag ( HF ) will be reset to high after Reset ( RS ).
WRITE ENABLE ( W )
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
isnotset.Dataset-upandholdtimesmustbeadheredtowithrespecttotherising
edgeoftheWriteEnable(W).DataisstoredintheRAMarraysequentiallyand
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation,theHalf-FullFlag(HF)willbesettolowandwillremainsetuntilthe
difference between the write pointer and read pointer is less than or equal to
onehalfofthetotalmemoryofthedevice.TheHalf-FullFlag(HF)isthenreset
by the rising edge of the read operation.
Topreventdataoverflow,theFullFlag(FF)willgolow,inhibitingfurtherwrite
operations. Upon the completion of a valid read operation, the Full Flag (FF)
willgohighaftertRFF,allowingavalidwritetobegin.WhentheFIFOisfull,the
internalwritepointerisblockedfromW,soexternalchangesinWwillnotaffect
the FIFO when it is full.
READ ENABLE ( R )
AreadcycleisinitiatedonthefallingedgeoftheReadEnable(R)provided
theEmptyFlag(EF)isnotset.ThedataisaccessedonaFirst-In/First-Outbasis,
independentofanyongoingwriteoperations.AfterReadEnable(R)goeshigh,
the Data Outputs (Q0– Q8) will return to a high impedance condition until the
next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go low, allowing the “final” read cycle but inhibiting further read
operationswiththedataoutputsremaininginahighimpedancestate.Oncea
validwriteoperationhasbeenaccomplished,theEmptyFlag(EF)willgohigh
aftertWEFandavalidReadcanthenbegin.WhentheFIFOisempty,theinternal
readpointerisblockedfromRsoexternalchangesinRwillnotaffecttheFIFO
when it is empty.
FIRST LOAD/RETRANSMIT ( FL/RT )
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the
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