參數(shù)資料
型號： IDT72V831L15PF
廠商： IDT, Integrated Device Technology Inc
文件頁數(shù)： 1/16頁
文件大?。?/td> 0K
描述： IC SYNC FIFO 2048X9 15NS 64QFP
標(biāo)準(zhǔn)包裝： 90
系列： 72V
功能： 異步
存儲容量： 18.4K（2K x 9）
數(shù)據(jù)速率： 67MHz
訪問時間： 15ns
電源電壓： 3 V ~ 3.6 V
工作溫度： 0°C ~ 70°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-TQFP（14x14）
包裝： 托盤
其它名稱： 72V831L15PF
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3 VOLT DUAL CMOS SyncFIFO
DUAL 256 X 9, DUAL 512 X 9,
DUAL 1,024 X 9, DUAL 2,048 X 9,
DUAL 4,096 X 9 , DUAL 8,192 X 9
IDT72V801
IDT72V811
IDT72V821
IDT72V831
IDT72V841
IDT72V851
OCTOBER 2008
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4093/4
FEATURES:
The IDT72V801 is equivalent to two IDT72V201 256 x 9 FIFOs
The IDT72V811 is equivalent to two IDT72V211 512 x 9 FIFOs
The IDT72V821 is equivalent to two IDT72V221 1,024 x 9 FIFOs
The IDT72V831 is equivalent to two IDT72V231 2,048 x 9 FIFOs
The IDT72V841 is equivalent to two IDT72V241 4,096 x 9 FIFOs
The IDT72V851 is equivalent to two IDT72V251 8,192 x 9 FIFOs
Offers optimal combination of large capacity, high speed,
design flexibility and small footprint
Ideal for prioritization, bidirectional, and width expansion
applications
10 ns read/write cycle time
5V input tolerant
Separate control lines and data lines for each FIFO
Separate Empty, Full, programmable Almost-Empty and
Almost-Full flags for each FIFO
Enable puts output data lines in high-impedance state
Space-saving 64-pin plastic Thin Quad Flat Pack (TQFP/
STQFP)
Industrial temperature range (–40
°°°°°C to +85°°°°°C) is available
Green parts available, see ordering information
DESCRIPTION:
The IDT72V801/72V811/72V821/72V831/72V841/72V851/72V851 are
dual synchronous (clocked) FIFOs. The device is functionally equivalent to
two IDT72V201/72V211/72V221/72V231/72V241/72V251 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins.
Each of the two FIFOs (designated FIFO A and FIFO B) contained in the
IDT72V801/72V811/72V821/72V831/72V841/72V851 has a 9-bit input data
port (DA0 - DA8, DB0 - DB8) and a 9-bit output data port (QA0 - QA8,
QB0 - QB8). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and two Write Enable pins (
WENA1, WENA2, WENB1, WENB2).
DataiswrittenintoeachofthetwoarraysoneveryrisingclockedgeoftheWrite
Clock (WCLKA, WCLKB) when the appropriate Write Enable pins are
asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and two Read Enable pins (
RENA1, RENA2, RENB1,
RENB2).TheReadClockcanbetiedtotheWriteClockforsingleclockoperation
orthetwoclockscanrunasynchronousofoneanotherfordualclockoperation.
An Output Enable pin (
OEA, OEB) is provided on the read port of each FIFO
for three-state output control.
Each of the two FIFOs has two fixed flags, Empty (
EFA,EFB)andFull(FFA,
FFB). Twoprogrammableflags,Almost-Empty(PAEA,PAEB)andAlmost-Full
(
PAFA,PAFB),areprovidedforeachFIFObanktoimprovememoryutilization.
If not programmed, the programmable flags default to Empty+7 for
PAEAand
PAEB, and Full-7 for PAFA and PAFB.
The IDT72V801/72V811/72V821/72V831/72V841/72V851 architecture
lends itself to many flexible configurations such as:
2-level priority data buffering
Bidirectional operation
Width expansion
Depth expansion
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
WCLKA
WENA1
WENA2
DA0 - DA8
LDA
OFFSET REGISTER
INPUT REGISTER
WRITE CONTROL
LOGIC
RESET LOGIC
OUTPUT REGISTER
OEA
RSA
QA0 - QA8
RCLKA
RENA1
RENA2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFA
PAEA
PAFA
FFA
4093 drw 01
WCLKB
WENB1
WENB2
DB0 - DB8
LDB
OFFSET REGISTER
INPUT REGISTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
WRITE CONTROL
LOGIC
WRITE POINTER
RESET LOGIC
OUTPUT REGISTER
OEB
RSB
QB0 - QB8
RCLKB
RENB1
RENB2
READ CONTROL
LOGIC
READ POINTER
FLAG
LOGIC
EFB
PAFB
FFB
PAEB
WRITE POINTER
RAM ARRAY
256 x 9, 512 x 9,
1,024 x 9, 2,048 x 9,
4,096 x 9, 8,192 x 9
相關(guān)PDF資料
PDF描述
MS27656T15F5PC CONN RCPT 5POS WALL MNT W/PINS
IDT72V831L15TF IC SYNC FIFO 2048X9 15NS 64QFP
MS3111P14-5S CONN RCPT 5POS CBL MNT W/SCKT
VI-B63-IV-F2 CONVERTER MOD DC/DC 24V 150W
MS27472E10A99S CONN RCPT 7POS WALL MT W/SCKT
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT72V831L15PF8 功能描述:IC SYNC FIFO 2048X9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V831L15PFI 功能描述:IC SYNC FIFO 2048X9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V831L15PFI8 功能描述:IC SYNC FIFO 2048X9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V831L15TF 功能描述:IC SYNC FIFO 2048X9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
IDT72V831L15TF8 功能描述:IC SYNC FIFO 2048X9 15NS 64QFP RoHS:否 類別:集成電路 (IC) >> 邏輯 - FIFO 系列:72V 標(biāo)準(zhǔn)包裝:90 系列:7200 功能:同步 存儲容量:288K（16K x 18） 數(shù)據(jù)速率:100MHz 訪問時間:10ns 電源電壓:4.5 V ~ 5.5 V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:64-LQFP 供應(yīng)商設(shè)備封裝:64-TQFP（14x14） 包裝:托盤 其它名稱:72271LA10PF
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*